View STM32F205VET6_8150747.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. october 2014 docid15818 rev 12 1/179 stm32f205xx stm32f207xx arm-based 32-bit mcu, 150dmips, up to 1 mb flash/128+4kb ram, usb otg hs/fs, ethernet, 17 tims, 3 adcs, 15 comm. interfaces & camera datasheet - production data features ? core: arm ? 32-bit cortex ? -m3 cpu (120 mhz max) with adaptive real -time accelerator (art accelerator? allowing 0-wait state execution performance from flash memory, mpu, 150 dmips/1.25 dmips/mhz (dhrystone 2.1) ? memories ? up to 1 mbyte of flash memory ? 512 bytes of otp memory ? up to 128 + 4 kbytes of sram ? flexible static memory controller that supports compact flash, sram, psram, nor and nand memories ? lcd parallel interface, 8080/6800 modes ? clock, reset and supply management ? from 1.8 to 3.6 v application supply+i/os ? por, pdr, pvd and bor ? 4 to 26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? low-power modes ? sleep, stop and standby modes ?v bat supply for rtc, 20 32 bit backup registers, and optional 4 kb backup sram ? 3 12-bit, 0.5 s adcs with up to 24 channels and up to 6 msps in tr iple interleaved mode ? 2 12-bit d/a converters ? general-purpose dma: 16-stream controller with centralized fifos and burst support ? up to 17 timers ? up to twelve 16-bit and two 32-bit timers, up to 120 mhz, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? debug mode: serial wire debug (swd), jtag, and cortex-m3 embedded trace macrocell? ? up to 140 i/o ports with interrupt capability: ? up to 136 fast i/os up to 60 mhz ? up to 138 5 v-tolerant i/os ? up to 15 communica tion interfaces ? up to 3 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts and 2 uarts (7.5 mbit/s, iso 7816 interface, lin, irda, modem ctrl) ? up to 3 spis (30 mbit/s), 2 with muxed i 2 s to achieve audio class accuracy via audio pll or external pll ? 2 can interfaces (2.0b active) ? sdio interface ? advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full-speed phy and ulpi ? 10/100 ethernet mac with dedicated dma: supports ieee 1588v2 hardware, mii/rmii ? 8- to 14-bit paralle l camera interface (48 mbyte/s max.) ? crc calculation unit ? 96-bit unique id table 1. device summary reference part number stm32f205xx stm32f205rb, stm32f205rc, stm32f205re, stm32f205rf, stm32f205rg, stm32f205vb, stm32f205vc, stm32f205ve, stm32f205vf stm32f205vg, stm32f205zc, stm32f205ze, stm32f205zf, stm32f205zg stm32f207xx stm32f207ic, stm32f207ie, stm32f207if, stm32f207ig, stm32f207zc, stm32f207ze, stm32f207zf, stm32f207zg, stm32f207vc, stm32f207ve, stm32f207vf, stm32f207vg lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp144 (20 20 mm) lqfp176 (24 24 mm) ufbga176 (10 10 mm) wlcsp64+2 (0.400 mm pitch) &"'! www.st.com
contents stm32f20xxx 2/179 docid15818 rev 12 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 arm ? cortex?-m3 core with embedded flash and sram . . . . . . . . . . . 19 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 19 3.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20 3.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 22 3.11 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16.1 regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16.2 regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.16.3 regulator on/off and inte rnal reset on/off availability . . . . . . . . . . 29 3.17 real-time clock (rtc), backup sram and backup registers . . . . . . . . . . 29 3.18 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.19 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.20.1 advanced-control timers (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.20.2 general-purpose timers (timx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.20.3 basic timers tim6 and tim7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
docid15818 rev 12 3/179 stm32f20xxx contents 5 3.20.4 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20.5 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21 inter-integrated circuit interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.22 universal synchronous/asy nchronous receiver transmitters (uarts/usarts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.23 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.24 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.25 sdio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.26 ethernet mac interface with dedicated dma and ieee 1588 support . . . 35 3.27 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.28 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 36 3.29 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . . . 36 3.30 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.31 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.32 true random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.33 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.34 adcs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.35 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.36 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.37 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.38 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
contents stm32f20xxx 4/179 docid15818 rev 12 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.2 vcap1/vcap2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.3 operating conditions at power-up / power-down (regulator on) . . . . . . 74 6.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 74 6.3.5 embedded reset and power control bloc k characteristics . . . . . . . . . . . 75 6.3.6 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.7 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.8 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.9 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.10 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.11 pll spread spectrum clock generatio n (sscg) characteristics . . . . . . 96 6.3.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.13 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.14 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 101 6.3.15 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.16 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.17 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.18 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.20 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.3.21 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.24 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.25 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.26 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 149 6.3.27 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 149 6.3.28 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.1.1 lqfp64, 10 x 10 mm 64 pin low-profile quad flat package . . . . . . . . . 151 7.1.2 wlcsp64+2 - 0.400 mm pitch wafer level chip size package . . . . . . 153 7.1.3 lqfp100, 14 x 14 mm 100-pin low-profile quad flat package . . . . . . . 154
docid15818 rev 12 5/179 stm32f20xxx contents 5 7.1.4 lqfp144, 20 x 20 mm 144-pin low-profile quad flat package . . . . . . . 157 7.1.5 lqfp176, 24 24 176-pin low profile quad flat package . . . . . . . . . . 160 7.1.6 ufbga176+25 10 10 mm ultra thin fine pitch ball grid array . . . . . . 163 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
list of tables stm32f20xxx 6/179 docid15818 rev 12 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f205xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. stm32f207xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. regulator on/off and internal reset on/off availability. . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 8. stm32f20x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 9. fsmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 10. alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 11. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 12. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 13. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 14. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 15. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 72 table 16. vcap1/vcap2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 17. operating conditions at power-up / power-down (r egulator on) . . . . . . . . . . . . . . . . . . . . 74 table 18. operating conditions at power-up / power-down (r egulator off). . . . . . . . . . . . . . . . . . . . 74 table 19. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 20. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabl ed) or ram . . . . . . . . . . . . . . . . . . . 77 table 21. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 22. typical and maximum current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 81 table 23. typical and maximum current consumptions in st op mode . . . . . . . . . . . . . . . . . . . . . . . . 83 table 24. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 84 table 25. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . . 84 table 26. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 27. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 28. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 29. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 30. hse 4-26 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 0 table 31. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 32. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 33. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 34. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 35. plli2s (audio pll) characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 36. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 37. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 38. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 39. flash memory programming with v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 40. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 41. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 42. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 43. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1 table 44. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 45. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 46. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
docid15818 rev 12 7/179 stm32f20xxx list of tables 7 table 47. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 48. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 49. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 50. characteristics of timx connected to the apb1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 51. characteristics of timx connected to the apb2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 52. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 53. scl frequency (f pclk1 = 30 mhz.,v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 54. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 55. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 56. usb otg fs startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 57. usb otg fs dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 58. usb otg fs electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 59. usb hs dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 table 60. clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 61. ulpi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 62. ethernet dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 63. dynamics characteristics: ethe rnet mac signals for smi. . . . . . . . . . . . . . . . . . . . . . . . . 121 table 64. dynamics characteristics: ethe rnet mac signals for rmii . . . . . . . . . . . . . . . . . . . . . . . . 121 table 65. dynamics characteristics: ethe rnet mac signals for mii . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 66. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 67. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 68. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 69. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 table 70. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 71. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 72. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . 131 table 73. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 132 table 74. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 75. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 76. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 77. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 78. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 139 table 79. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 80. switching characteristics for pc card/cf read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 81. switching characteristics for pc card/cf read and write cycles in i/o space . . . . . . . . . 146 table 82. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 83. switching characteristics for na nd flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 84. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 85. sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 86. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 87. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 151 table 88. wlcsp64+2 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 89. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 155 table 90. lqfp144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data. . . . . . . . 157 table 91. lqfp176 - low profile quad flat package 24 24 1.4 mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 92. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data . 163 table 93. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 94. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 95. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
list of figures stm32f20xxx 8/179 docid15818 rev 12 list of figures figure 1. compatible board design between stm32f10xx and stm32f2xx for lqfp64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 2. compatible board design between stm32f10xx and stm32f2xx for lqfp100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. compatible board design between stm32f10xx and stm32f2xx for lqfp144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4. stm32f20x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6. regulator off/internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. regulator off/internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9. startup in regulator off: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 28 figure 10. stm32f20x lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 11. stm32f20x wlcsp64+2 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 12. stm32f20x lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 13. stm32f20x lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 14. stm32f20x lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15. stm32f20x ufbga176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 figure 16. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 17. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 18. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 19. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 20. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 21. number of wait states versus f cpu and v dd range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 22. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 23. typical current consumption vs temperature, run mode, code with data processing running from ram, and peripherals on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 24. typical current consumption vs temperature, run mode, code with data processing running from ram, and peripherals off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 25. typical current consumption vs temperature, run mode, code with data processing running from flash, art accelerator o ff, peripherals on . . . . . . . . . . . . . . . 80 figure 26. typical current consumption vs temperature, run mode, code with data processing running from flash, art accelerator o ff, peripherals off . . . . . . . . . . . . . . 80 figure 27. typical current consumption vs temperature in sleep mode, peripherals on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 28. typical current consumption vs temperature in sleep mode, peripherals off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 29. typical current consumption vs temperature in st op mode . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 30. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 31. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 32. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 33. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 34. acc hsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 35. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 36. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 37. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
docid15818 rev 12 9/179 stm32f20xxx list of figures 10 figure 38. ft i/o input ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 39. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 40. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 41. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 42. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 43. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 44. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 15 figure 45. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 46. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 47. usb otg fs timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 119 figure 48. ulpi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 49. ethernet smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 50. ethernet rmii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 51. ethernet mii timing di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 52. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 53. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 54. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 126 figure 55. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 126 figure 56. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 57. asynchronous non-multip lexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 131 figure 58. asynchronous non-multip lexed sram/psram/nor write wavefo rms . . . . . . . . . . . . . . 132 figure 59. asynchronous multiplexed psram/nor read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . 133 figure 60. asynchronous multiplexed psram/nor write wave forms . . . . . . . . . . . . . . . . . . . . . . . 135 figure 61. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 62. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 63. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 64. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 65. pc card/compactflash controller waveforms for common me mory read access . . . . . . 141 figure 66. pc card/compactflash controller waveforms for common me mory write access . . . . . . 142 figure 67. pc card/compactflash controlle r waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 68. pc card/compactflash controlle r waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 69. pc card/compactflash cont roller waveforms for i/o space read access . . . . . . . . . . . . 144 figure 70. pc card/compactflash cont roller waveforms for i/o space write access . . . . . . . . . . . . 145 figure 71. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 72. nand controller waveforms for wr ite access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 73. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 148 figure 74. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 148 figure 75. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 76. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 77. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 151 figure 78. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 79. wlcsp64+2 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . 153 figure 80. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 154 figure 81. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 82. lqfp100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 83. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 84. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 85. lqfp144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 86. lqfp176 - low profile quad flat package 24 24 1.4 mm, package outline . . . . . . . . 160
list of figures stm32f20xxx 10/179 docid15818 rev 12 figure 87. lqfp176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 88. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
docid15818 rev 12 11/179 stm32f20xxx introduction 178 1 introduction this datasheet provides the description of the stm32f205xx and stm32f207xx lines of microcontrollers. for more details on the whole stmicroelectronics stm32? family, please refer to section 2.1: full compatibilit y throughout the family . the stm32f205xx and stm32f207xx datasheet should be read in conjunction with the stm32f20x/stm32f21x reference manual. they will be referred to as stm32f20x devices throughout the document. for information on programming, erasing and protection of the internal flash memory, please refer to the stm32f20x/stm32f21x flash programming manual (pm0059). the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com . for information on the cortex ? -m3 core please refer to the cortex ? -m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/inde x.jsp?topic=/com.arm.doc.ddi0337e/.
description stm32f20xxx 12/179 docid15818 rev 12 2 description the stm32f20x family is based on the high-performance arm ? cortex ? -m3 32-bit risc core operating at a frequency of up to 1 20 mhz. the family incorporates high-speed embedded memories (flash memory up to 1 mb yte, up to 128 kbytes of system sram), up to 4 kbytes of backup sram, and an extensive range of enhanced i/os and peripherals connected to two apb buses, three ahb buses and a 32-bit multi-ahb bus matrix. the devices also feature an adaptive real-t ime memory accelerator (art accelerator?) which allows to achieve a performance equivale nt to 0 wait state program execution from flash memory at a cpu frequency up to 120 mhz. this performance has been validated using the coremark benchmark. all devices offer three 12-bit adcs, two dacs, a low-power rtc, twelve general-purpose 16-bit timers including two pwm timers for mo tor control, two general-purpose 32-bit timers. a true number random generator (rng). they also feature standard and advanced communication interfaces. new advanced peripherals include an sdio, an enhanced flexible static memory control (fsmc) interface (for devices offered in packages of 100 pins and more), and a camera interface for cmos sensors. the devices also feature standard peripherals. ? up to three i 2 cs ? three spis, two i 2 ss. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external pll to allow synchronization. ? 4 usarts and 2 uarts ? a usb otg high-speed with full-sp eed capability (with the ulpi) ? a second usb otg (full-speed) ? two cans ? an sdio interface ? ethernet and camera interface available on stm32f207xx devices only. note: the stm32f205xx and stm32f207xx devices operate in the ?40 to +105 c temperature range from a 1.8 v to 3.6 v power supply. on devices in wlcsp64+2 package, if irroff is set to v dd, the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range using an external power supply supervisor (see section 3.16 ). a comprehensive set of power- saving modes allow the design of low-power applications. stm32f205xx and stm32f207xx devices are offered in various packages ranging from 64 pins to 176 pins. the set of included peri pherals changes with the device chosen.these features make the stm32f205xx and stm32f207xx microcontroller family suitable for a wide range of applications: ? motor drive and application control ? medical equipment ? industrial applications: plc, inverters, circuit breakers ? printers, and scanners ? alarm systems, video intercom, and hvac ? home audio appliances figure 4 shows the general block diagram of the device family.
stm32f20xxx description docid15818 rev 12 13/179 table 2. stm32f205xx features and peripheral counts peripherals stm32f205rx stm32f205vx stm32f205zx flash memory in kbytes 128 256 512 768 1024 128 256 512 768 1024 256 512 768 1024 sram in kbytes system (sram1+sram2) 64 (48+16) 96 (80+16) 128 (112+16) 64 (48+16) 96 (80+16) 128 (112+16) 96 (80+16) 128 (112+16) backup 4 4 4 fsmc memory controller no yes (1) ethernet no timers general-purpose 10 advanced-control 2 basic 2 iwdg yes wwdg yes rtc yes random number generator yes comm. interfaces spi/(i 2 s) 3/(2) (2) i 2 c 3 usart uart 4 2 usb otg fs yes usb otg hs yes can 2 camera interface no gpios 51 82 114 sdio yes 12-bit adc number of channels 3 16 16 24 12-bit dac number of channels yes 2 maximum cpu frequency 120 mhz operating voltage 1.8 v to 3.6 v (3)
description stm32f20xxx 14/179 docid15818 rev 12 operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c package lqfp64 lqfp64 wlcsp64 +2 lqfp6 4 lqfp64 wlcsp6 4+2 lqfp100 lqfp144 1. for the lqfp100 package, only fsmc bank1 or bank2 are available. b ank1 can only support a multiplexed nor/psram memory using the ne1 chip select. bank2 can only support a 16- or 8-bi t nand flash memory using the nce2 chip select. the interrupt line cannot be used s ince port g is not available in this package. 2. the spi2 and spi3 interfaces give the flexibility to work in an exclusive way in either the spi mode or the i2s audio mode. 3. on devices in wlcsp64+2 package, if irroff is set to v dd , the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range using an external power supply supervisor (see section 3.16 ). table 3. stm32f207xx features and peripheral counts peripherals stm32f207vx stm32f207zx stm32f207ix flash memory in kbytes 256 512 768 1024 256 512 768 1024 256 512 768 1024 sram in kbytes system (sram1+sram2) 128 (112+16) backup 4 fsmc memory controller yes (1) ethernet yes timers general-purpose 10 advanced-control 2 basic 2 iwdg yes wwdg yes rtc yes random number generator yes table 2. stm32f205xx features and peripheral counts (continued) peripherals stm32f205rx stm32f205vx stm32f205zx
stm32f20xxx description docid15818 rev 12 15/179 comm. interfaces spi/(i 2 s) 3/(2) (2) i 2 c 3 usart uart 4 2 usb otg fs yes usb otg hs yes can 2 camera interface yes gpios 82 114 140 sdio yes 12-bit adc number of channels 3 16 24 24 12-bit dac number of channels yes 2 maximum cpu frequency 120 mhz operating voltage 1.8 v to 3.6 v (3) operating temperatures ambient temperatures: ?40 to +85 c/?40 to +105 c junction temperature: ?40 to + 125 c package lqfp100 lqfp144 lqfp176/ ufbga176 1. for the lqfp100 package, only fsmc bank1 or bank2 are available. bank 1 can only support a multiplex ed nor/psram memory using the ne1 chip select. bank2 can only support a 16- or 8-bit nand flash memory using the nce2 chip se lect. the interrupt line cannot be used s ince port g is not available in this package. 2. the spi2 and spi3 interfaces give the flexibility to work in an exclusive way in either the spi mode or the i2s audio mode. 3. on devices in wlcsp64+2 package, if irroff is set to v dd , the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range using an external pow er supply supervisor (see section 3.16 ). table 3. stm32f207xx features and peripheral counts (continued) peripherals stm32f207vx stm32f207zx stm32f207ix
description stm32f20xxx 16/179 docid15818 rev 12 2.1 full compatibility throughout the family the stm32f205xx and stm32f207xx constitute the stm32f20x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. the stm32f205xx and stm32f 207xx devices maintain a close compatibility with the whole stm32f10xxx family. all functional pins are pin-to-pin compatible. the stm32f205xx and stm32f207xx, however, are not drop-in replacements for the stm32f10xxx devices: the two families do not have the same power scheme, and so their power pins are different. nonetheless, transition from the stm32f10xxx to the stm32f20x family remains simple as only a few pins are impacted. figure 3 and figure 1 provide compatible board designs between the stm32f20x and the stm32f10xxx family. figure 1. compatible board design between stm32f10xx and stm32f2xx for lqfp64 package 6 33 6 33 6 33 6 33 ? resistororsolderingbridge presentforthe34-&xx configurationnotpresentinthe 34-&xxconfiguration aib
docid15818 rev 12 17/179 stm32f20xxx description 178 figure 2. compatible board design between stm32f10xx and stm32f2xx for lqfp100 package figure 3. compatible board design between stm32f10xx and stm32f2xx for lqfp144 package 1. rfu = reserved for future use. aic 6 33 6 33 6 $$ 6 33 6 33 6 33 : resistororsolderingbridge presentforthe34-&xx configurationnotpresentinthe 34-&xxconfiguration 2&5 6 33 6 $$ 6 33 for34-&xx 6 $$ for34-&xx 4wo : resistorsconnectedto 6 33 forthe34-&xx 6 $$ 6 33 or.#forthe34-&xx aic 6 33 : resistororsolderingbridge presentforthe34-&xx configurationnotpresentinthe 34-&xxconfiguration 6 33 4wo : resistorsconnectedto 6 33 6 $$ 6 33 6 33 2&5 6 33 6 $$ 6 33 forthe34-&xx 6 $$ 6 33 or.#forthe34-&xx
description stm32f20xxx 18/179 docid15818 rev 12 figure 4. stm32f20x block diagram 1. the timers connected to apb2 are clock ed from timxclk up to 120 mhz, while the timers connected to apb1 are clocked from timxclk up to 60 mhz. 2. the camera interface and ethernet are available only in stm32f207xx devices. '0)/0/24! !("!0" %84)47+50 !& 0!;= '0)/0/24" 0";= 4)-07- complchannels4)-?#(;=. channels4)-?#(;= %42 "+).as!& 4)-07- '0)/0/24# 0#;= 53!24 2848#+ #43243as!& '0)/0/24$ 0$;= '0)/0/24% 0%;= '0)/0/24& 0&;= '0)/0/24' 0';= 30) -/3)-)3/ 3#+.33as!& !0"-(z !0"-(z analoginputscommon tothe!$#s analoginputscommon tothe!$# 6 $$2%&?!$# analoginputsto!$# channels%42as!& channels%42as!& channels%42as!& channels 2848#+ 53!24 2848#+ 53!24 2848as!& 5!24 2848as!& 5!24 -/3)$/54 -)3/$).3#+#+ 30))3 .3373-#+as!& -/3)$/54 -)3/$).3#+#+ 30))3 .3373-#+as!& 3#,3$!3-"!as!& )#3-"53 3#,3$!3-"!as!& )#3-"53 4828 bx#!. 4828 bx#!. $!#?/54 as!& $!#?/54 as!& )4& 77$' +""+302!- 24#?!& /3#?). /3#?). /3#?/54 /3#?/54 .234 6 $$! 6 33! 6 #!0 6 #!0 53!24 2848#+ #43243as!& smcard ir$! smcard ir$! smcard ir$! smcard ir$! b b b b b b b b #43243as!& #43243as!& 3$)/--# $;= #-$#+as!& 6 "!4 to6 $-! !("!0" $-! 3#,3$!3-"!as!& )#3-"53 '0)/0/24( 0(;= '0)/0/24) 0);= *4!'37 $ "53 3 "53 ) "53 .6)# %4- -05 .*4234*4$) *4$/37$ *4$/42!#%37/ 42!#%#,+ 42!#%$;= *4#+37#,+ %thernet-!# $-! -))or2-))as!& -$)/as!& &)&/ 53" $-! &)&/ /4' (3 $0$- 5,0)#+$ $)2340.84 $-! 3treams &)&/ $-! 3treams &)&/ !##%, #!#(% 32!-+" 32!-+" #,+.%;=!;= $;=/%.7%. .",;=.,.2%' .7!)4)/2$9#$ .)/2$)/72).4;= ).4..))3as!& 3#,3$!).4.)$6"533/& #amera interface (39.#639.# 0)8#,+$;= 53" 0(9 /4'&3 $0 $- &)&/ &)&/ !("-(z 0(9 &)&/ 53!24-"ps 4emperaturesensor !$# !$# !$# )& )& 6$$! 6$$! 0/20$2 3upply 6$$! supervision 06$ 2eset )nt 0/2 84!,/3# -(z 84!,k(z (#,+x -!.!'4 24# 2#(3 &#,+ 2#,3 072 )7$' 6 "!4 6$$! 6$$ !75 2eset clock control 0,, 0#,+x interface 6 $$ to6 6 33 6oltage regulator 6to6 6 $$ 0owermanagmt 6$$ 24#?!& "ackup register 3#,3$!).4.)$6"533/& !("bus matrix3- !0"-(z !("-(z ,3 ,3 channelsas!& channel as!& channel as!& 4)- b b b 4)- channelsas!& 4)- channelas!& b b 4)- channelas!& b "/2 $!# $!# &lash -byte 32!-032!-./2&lash 0##ard!4! .!.$&lash %xternalmemory controller&3-# 4)- 4)- 4)- 4)- 4)- 4)- 4)- 4)- aic complchannels4)-?#(;=. channels4)-?#(;= %42 "+).as!& &)&/ 2.' !2-#ortex - -(z !24accelerator !0"-(z !("
docid15818 rev 12 19/179 stm32f20xxx functional overview 178 3 functional overview 3.1 arm ? cortex ? -m3 core with embedded flash and sram the arm cortex-m3 processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm cortex-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. with its embedded arm core, the stm32f20x fa mily is compatible with all arm tools and software. figure 4 shows the general block diagram of the stm32f20x family. 3.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex ? -m3 processors. it balances the in herent performance advantage of the arm cortex-m3 over flash memory te chnologies, which normally requires the processor to wait for the flash memory at higher operating frequencies. to release the processor full 150 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 120 mhz. 3.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it.
functional overview stm32f20xxx 20/179 docid15818 rev 12 3.4 embedded flash memory the stm32f20x devices embed a 128-bit wide flash memory of 128 kbytes, 256 kbytes, 512 kbytes, 768 kbytes or 1 mbytes av ailable for storing programs and data. the devices also feature 512 bytes of otp memo ry that can be used to store critical user data such as ethernet mac a ddresses or cryp tographic keys. 3.5 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the c rc calculation unit help s compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 embedded sram all stm32f20x products embed: ? up to 128 kbytes of system sram access ed (read/write) at cp u clock speed with 0 wait states ? 4 kbytes of backup sram. the content of this area is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 3.7 multi-ahb bus matrix the 32-bit multi-ahb bu s matrix interconnects all the ma sters (cpu, dmas, ethernet, usb hs) and the slaves (flash me mory, ram, fsmc, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.
docid15818 rev 12 21/179 stm32f20xxx functional overview 178 figure 5. multi-ahb matrix 3.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. they sh are some centralized fifos for apb/ahb peripherals, support burst transfer and are de signed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which autom ates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. !2- #ortex - '0 $-! '0 $-! -!# %thernet 53"/4' (3 "usmatrix 3 3 3 3 3 3 3 3 3 )#/$% $#/$% !24 !##%, &lash memory 32!- +byte 32!- +byte !(" periph !(" periph &3-# 3tatic-em#tl - - - - - - - ) bus $ bus 3 bus $-!?0 $-!?-%- $-!?-%- $-!?0 %4(%2.%4?- 53"?(3?- aic !0" !0"
functional overview stm32f20xxx 22/179 docid15818 rev 12 the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart and uart ? general-purpose, basic and advanced-control timers timx ? dac ? sdio ? camera interface (dcmi) ? adc. 3.9 flexible static me mory controller (fsmc) the fsmc is embedded in all stm32f20x devi ces. it has four chip select outputs supporting the following modes: pc card/c ompact flash, sram, psram, nor flash and nand flash. functionality overview: ? write fifo ? code execution from external memory except for nand flash and pc card ? maximum frequency (f hclk ) for external access is 60 mhz lcd parallel interface the fsmc can be configured to interface seam lessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 nested vectored inter rupt controller (nvic) the stm32f20x devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the cortex ? -m3. the nvic main features are the following: ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency.
docid15818 rev 12 23/179 stm32f20xxx functional overview 178 3.11 external interrupt /event controller (exti) the external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 140 gpios can be connected to the 16 external interrupt lines. 3.12 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-trimmed to offer 1% accuracy. the application can then select as system clock either the rc osc illator or an external 4-26 mhz clock source. this clock is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r and a software interrupt is ge nerated (if enabl ed). similarly, full interrupt management of the pll clock entry is available when necessary (for example if an indirectly used ex ternal oscillator fails). the advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. in particular, the ethernet and usb otg fs periph erals can be clocked by the system clock. several prescalers and plls allow the conf iguration of the three ahb buses, the high- speed apb (apb2) and the low- speed apb (apb1) domains. the maximum frequency of the three ahb buses is 120 mh z and the maximum frequency the high-speed apb domains is 60 mhz. the maximum allo wed frequency of the low-speed apb do main is 30 mhz. the devices embed a dedicate pll (plli2s) which allow to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz. 3.13 boot modes at startup, boot pins are used to select one out of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10), usart3 (pc10/pc 11 or pb10/pb11), can2 (pb5/pb13), usb otg fs in device mode (pa11/pa12) through dfu (device firmware upgrade). 3.14 power supply schemes ? v dd = 1.8 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. on devices in wlcsp64+2 package, if irroff is set to v dd , the supply voltage can drop to 1.7 v when the device operates
functional overview stm32f20xxx 24/179 docid15818 rev 12 in the 0 to 70 c temperature range using an external power supply supervisor (see section 3.16 ). ? v ssa , v dda = 1.8 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock, 32 khz oscillator and backup registers (through power switch) when v dd is not present. refer to figure 19: power supply scheme for more details. 3.15 power supply supervisor the devices have an integrated power-on reset (por) / power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por/pdr is always active and ensu res proper operation starting from 1.8 v. after the 1.8 v por threshold level is reached, the option byte loading process starts, either to confirm or modify default bor threshold levels, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset ci rcuit. on devices in wlcsp64+2 package, the bor, por and pdr features can be disabled by setting irroff pin to v dd . in this mode an external power supply supervisor is required (see section 3.16 ). the devices also feature an embedded progra mmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.16 voltage regulator the regulator has five operating modes: ? regulator on ? main regulator mode (mr) ? low-power regulator (lpr) ? power-down ? regulator off ? regulator off/internal reset on ? regulator off/internal reset off 3.16.1 regulator on the regulator on modes are activated by default on lqfp packages.on wlcsp64+2 package, they are activated by connect ing both regoff and irroff pins to v ss , while only regoff must be connected to v ss on ufbga176 package (irroff is not available). v dd minimum value is 1.8 v.
docid15818 rev 12 25/179 stm32f20xxx functional overview 178 there are three power modes configured by software when the regulator is on: ? mr is used in the nominal regulation mode ? lpr is used in stop modes the lp regulator mode is configured by software when entering stop mode. ? power-down is used in standby mode. the power-down mode is activated only when entering standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of th e registers and sram are lost). two external ceramic capacitors should be connected on v cap_1 and v cap_2 pin. refer to figure 19: power supply scheme and table 16: vcap1/vcap2 operating conditions . all packages have the regulator on feature. 3.16.2 regulator off this feature is available only on packages featuring the regoff pi n. the regulator is disabled by holding regoff high. the regulator off mode allows to supply externally a v12 voltage source through v cap_1 and v cap_2 pins. the two 2.2 f ceramic capacitors should be replaced by two 100 nf decoupling capacitors. refer to figure 19: power supply scheme . when the regulator is off, there is no more internal monitoring on v12. an external power supply supervisor should be used to monito r the v12 of the logic power domain. pa0 pin should be used for this purpose, and act as power-on reset on v12 power domain. in regulator off mode, the following features are no more supported: ? pa0 cannot be used as a gpio pin since it a llows to reset the part of the 1.2 v logic power domain which is not reset by the nrst pin. ? as long as pa0 is kept low, the debug mode cannot be used at power-on reset. as a consequence, pa0 and nrst pins must be managed separately if the debug connection at reset or pre-reset is required. regulator off/internal reset on on wlcsp64+2 package, this mode is ac tivated by connecting regoff pin to v dd and irroff pin to v ss . on ufbga176 package, only regoff must be connected to v dd (irroff not available). in this mode, v dd /v dda minimum value is 1.8 v. the regulator off/internal rese t on mode allows to supply externally a 1.2 v voltage source through v cap_1 and v cap_2 pins, in addition to v dd .
functional overview stm32f20xxx 26/179 docid15818 rev 12 figure 6. regulator off/internal reset on the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach 1.08 v is faster than the time for v dd to reach 1.8 v, then pa0 should be kept low to cover both conditions: until v cap_1 and v cap_2 reach 1.08 v and until v dd reaches 1.8 v (see figure 8 ). ? otherwise, if the time for v cap_1 and v cap_2 to reach 1.08 v is slower than the time for v dd to reach 1.8 v, then pa0 should be asserted low externally (see figure 9 ). ? if v cap_1 and v cap_2 go below 1.08 v and v dd is higher than 1.8 v , then a reset must be asserted on pa0 pin. regulator off/internal reset off on wlcsp64+2 package, this mode activated by connecting regoff to v ss and irroff to v dd . irroff cannot be activated in conjunct ion with regoff. this mode is available only on the wlcsp64+2 package. it allows to supply externally a 1.2 v voltage source through v cap_1 and v cap_2 pins. in this mode, the integrated power-on reset (por)/ power- down reset (pdr) circuitry is disabled. an external power supply supervisor should mo nitor both the external 1.2 v and the external v dd supply voltage, and should maintain the device in reset mode as long as they remain below a specified threshold. the v dd specified threshold, belo w which the device must be maintained under reset, is 1.8 v. this supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range. a comprehensive set of power-saving modes allows to design low-power applications. aib 2%'/&& 6#!0? 6#!0? 0! 6 6 $$ to6 0ower downresetrisen before6#!0?6#!0?stabilization .234 )22/&& 6$$ !pplicationreset signaloptional %xternal6#!0? powersupplysupervisor %xtresetcontrolleractive when6#!0?6
docid15818 rev 12 27/179 stm32f20xxx functional overview 178 figure 7. regulator off/internal reset off the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains (see figure 8 ). ? pa0 should be kept low to cover both conditions: until v cap_1 and v cap_2 reach 1.08 v, and until v dd reaches 1.7 v. ? nrst should be controlled by an external reset controller to keep the device under reset when v dd is below 1.7 v (see figure 9 ). in this mode, when the internal reset is off, the following integrated features are no more supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled. ? the brownout reset (bor) circuitry is disabled. ? the embedded programmable voltage detector (pvd) is disabled. ? v bat functionality is no more available and v bat pin should be connected to vdd. 2%'/&& 6#!0? aib 6#!0? .234 6 )22/&& 6$$ 6 6$$ %xternal6$$6#!0? powersupplysupervisor %xtresetcontrolleractive when6$$6and 6#!0?6 0!
functional overview stm32f20xxx 28/179 docid15818 rev 12 figure 8. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid both whatever the internal reset mode (on or off). figure 9. startup in regulator off: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 6 $$ time 6 0$26 6 #!0? 6 #!0? 6 time 0!tiedto.234 .234 6 $$ time 6 0$26 6 #!0? 6 #!0? 6 time 0!assertedexternally .234
docid15818 rev 12 29/179 stm32f20xxx functional overview 178 3.16.3 regulator on/off and inte rnal reset on/off availability 3.17 real-time clock (r tc), backup sram an d backup registers the backup domain of the stm32f20x devices includes: ? the real-time clock (rtc) ? 4 kbytes of backup sram ? 20 backup registers the real-time clock (rtc) is an independent bc d timer/counter. its main features are the following: ? dedicated registers contain the second, minu te, hour (in 12/24 hour), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap year), 30, and 31 day of the month. ? programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. ? it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low- power rc oscillator or the hi gh-speed external clock divided by 128. the internal low- speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. ? two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for al arm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automati c wakeup and periodic alarms from every 120 s to every 36 hours. ? a 20-bit prescaler is used for the time base clock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. the 4-kbyte backup sram is an eeprom-like area.it can be used to store data which need to be retained in vbat and standby mode.this memory area is disabled to minimize power consumption (see section 3.18: low-power modes ). it can be enabled by software. table 4. regulator on/off and in ternal reset on/off availability package regulator on/internal reset on regulator off/internal reset on regulator off/internal reset off lqfp64 lqfp100 lqfp144 lqfp176 yes no no wlcsp 64+2 yes regoff and irroff set to v ss yes regoff set to v dd and irroff set to v ss yes regoff set to v ss and irroff set to v dd ufbga176 yes regoff set to v ss yes regoff set to v dd no
functional overview stm32f20xxx 30/179 docid15818 rev 12 the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 3.18: low-power modes ). like backup sram, the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or the v bat pin. 3.18 low-power modes the stm32f20x family supports three low-power modes to achieve the best compromise between low-power consumption, short st artup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from the stop mode by any of the exti line. the exti line source can be one of the 16 external lines , the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup or the ethernet wakeup. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, the sram and register conten ts are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm / wakeup / tamper /time stamp event occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped when the device enters the stop or standby mode. 3.19 v bat operation the v bat pin allows to power the device v bat domain from an external battery or an external supercapacitor. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation. when using wlcsp64+2 package, if irroff pin is connected to v dd , the v bat functionality is no more available and v bat pin should be connected to v dd .
docid15818 rev 12 31/179 stm32f20xxx functional overview 178 3.20 timers and watchdogs the stm32f20x devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode. table 5 compares the features of the advanced-c ontrol, general-purpose and basic timers. 3.20.1 advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary output max interface clock max timer clock advanced- control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes 60 mhz 120 mhz general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 30 mhz 60 mhz tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 30 mhz 60 mhz basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 30 mhz 60 mhz general purpose tim9 16-bit up any integer between 1 and 65536 no 2 no 60 mhz 120 mhz tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no 60 mhz 120 mhz tim12 16-bit up any integer between 1 and 65536 no 2 no 30 mhz 60 mhz tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no 30 mhz 60 mhz
functional overview stm32f20xxx 32/179 docid15818 rev 12 if configured as standard 16-bit timers, they ha ve the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). the tim1 and tim8 counters can be frozen in debug mode. many of the advanced-control timer features are shared with those of the st andard timx timers which have the same architecture. the advanced-control timer can th erefore work together with the timx timers via the timer link feature for sy nchronization or event chaining. 3.20.2 general-purpose timers (timx) there are ten synchronizable general-purpose timers embedded in the stm32f20x devices (see table 5 for differences). tim2, tim3, tim4, tim5 the stm32f20x include 4 full-featured general-purpose timers. tim2 and tim5 are 32-bit timers, and tim3 and tim4 are 16-bit timers. the tim2 and tim5 timers are based on a 32- bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16-bit auto-reload up/downcounter an d a 16-bit prescaler. they all feature 4 independent channels for input capture/output compare, pwm or one-pulse mode output. this gives up to 16 input capture/output compare/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose ti mers can work together, or with the other general-purpose timers and the advanced-control timers tim1 and tim8 via the timer link feature for synchronizat ion or event chaining. the counters of tim2, tim3, tim4, tim5 can be frozen in debug mode. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have independent dma request generation. they are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall- effect sensors. tim10, tim11 and tim9 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10 and tim11 feature one independent channel, wher eas tim9 has two independent channels for input capture/output compare, pwm or one-pu lse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. tim12, tim13 and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim13 and tim14 feature one independent channel, whereas tim12 has two independent channels for input capture/output compare, pwm or one-pu lse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 fu ll-featured general-purpose timers. they can also be used as simple time bases. 3.20.3 basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base.
docid15818 rev 12 33/179 stm32f20xxx functional overview 178 3.20.4 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. the counter can be frozen in debug mode. 3.20.5 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.20.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source 3.21 inter-integrated ci rcuit interface (i2c) up to three i 2 c bus interfaces can operate in multimaster and slave modes. they can support the standard- and fast-modes. they su pport the 7/10-bit addr essing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. 3.22 universal synchronous/asynch ronous receiver transmitters (uarts/usarts) the stm32f20x devices embed four univer sal synchronous/asynchronous receiver transmitters (usart1, usart2, usart3 and usart6) and two universal asynchronous receiver transmitters (uart4 and uart5). these six interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 and u sart6 interfaces are able to communicate at speeds of up to 7.5 mbit/s. th e other available interf aces communicate at up to 3.75 mbit/s. usart1, usart2, usart3 and usart6 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like communication capability. all interf aces can be served by the dma controller.
functional overview stm32f20xxx 34/179 docid15818 rev 12 3.23 serial peripheral interface (spi) the stm32f20x devices feature up to three spi s in slave and master modes in full-duplex and simplex communication modes. spi1 can communicate at up to 30 mbits/s, while spi2 and spi3 can communicate at up to 15 mbit/s . the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card /mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operat e in ti mode for comm unications in master mode and slave mode. 3.24 inter-integr ated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available. they can operate in master or slave mode, in half -duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as input or output channels. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mo de, the master clock can be output to the external dac/codec at 256 times the sampling frequency. all i2sx interfaces can be served by the dma controller. 3.25 sdio an sd/sdio/mmc host interface is availabl e, that supports multimediacard system specification version 4.2 in three different da tabus modes: 1-bit (default), 4-bit and 8-bit. table 6. usart feature comparison usart name standard features modem (rts/cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s (oversampling by 16) max. baud rate in mbit/s (oversampling by 8) apb mapping usart1 x x x x x x 1.87 7.5 apb2 (max. 60 mhz) usart2 x x x x x x 1.87 3.75 apb1 (max. 30 mhz) usart3 x x x x x x 1.87 3.75 apb1 (max. 30 mhz) uart4 x - x - x - 1.87 3.75 apb1 (max. 30 mhz) uart5 x - x - x - 3.75 3.75 apb1 (max. 30 mhz) usart6 x x x x x x 3.75 7.5 apb2 (max. 60 mhz)
docid15818 rev 12 35/179 stm32f20xxx functional overview 178 the interface allows data transfer at up to 48 mhz in 8-bit mode, and is compliant with the sd memory card specification version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdi o/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is fully compliant with the ce-ata digital protocol rev1.1. 3.26 ethernet mac interface with dedicated dma and ieee 1588 support peripheral available only on the stm32f207xx devices. the stm32f207xx devices prov ide an ieee-802.3-20 02-compliant media access controller (mac) for ethernet lan communications through an industry-standard medium- independent interface (mii) or a reduced medium-independent interface (rmii). the stm32f207xx requires an external physical interface device (phy) to connect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connected to the stm32f207xx mii port using 17 signals for mii or 9 signals for rmii, and can be clocked using the 25 mhz (mii) or 50 mhz (rmii) output from the stm32f207xx. the stm32f207xx includes the following features: ? supports 10 and 100 mbit/s rates ? dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors (see the stm32f20x and stm32f21x reference manual for details) ? tagged mac frame support (vlan support) ? half-duplex (csma/cd) and full-duplex operation ? mac control sublayer (control frames) support ? 32-bit crc generation and removal ? several address filtering modes for physic al and multicast address (multicast and group addresses) ? 32-bit status code for each transmitted or received frame ? internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes , that is 4 kbytes in total ? supports hardware ptp (precision time protocol) in accordance with ieee 1588 2008 (ptp v2) with the time stamp compar ator connected to the tim2 input ? triggers interrupt when system time becomes greater than target time 3.27 controller area network (can) the two cans are compliant with the 2.0a and b (a ctive) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit id entifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
functional overview stm32f20xxx 36/179 docid15818 rev 12 can is used). the 256 bytes of sram whic h are allocated for each can are not shared with any other peripheral. 3.28 universal serial bus on -the-go full-speed (otg_fs) the devices embed an usb otg full-speed de vice/host/otg peripher al with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillato r. the major features are: ? combined rx and tx fifo size of 320 35 bits with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 4 bidirectional endpoints ? 8 host channels with periodic out support ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected ? internal fs otg phy support 3.29 universal serial bus on -the-go high-speed (otg_hs) the stm32f20x devices embed a usb otg high-speed (up to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transceivers for full-speed oper ation (12 mb/s) and features a utmi low-pin interface (ulpi) for high-speed operation (4 80 mb/s). when using the usb otg hs in hs mode, an external phy device con nected to the ulpi is required. the usb otg hs peripheral is compliant wit h the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillato r. the major features are: ? combined rx and tx fifo size of 102 4 35 bits with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 6 bidirectional endpoints ? 12 host channels with periodic out support ? internal fs otg phy support ? external hs or hs otg operation suppor ting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. ? internal usb dma ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected
docid15818 rev 12 37/179 stm32f20xxx functional overview 178 3.30 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s application. it allows to achieve error-free i 2 s sampling clock accuracy withou t compromising on the cpu performance, while using usb peripherals. the plli2s configuration can be modified to manage an i 2 s sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i2s flow with an external pll (or codec output). 3.31 digital camera interface (dcmi) the camera interface is not available in stm32f205xx devices. stm32f207xx products embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain up to 27 mbyt e/s at 27 mhz or 48 mbyte/s at 48 mhz. it features: ? programmable polarity for the input pixel clock and synchronization signals ? parallel data communication can be 8-, 10-, 12- or 14-bit ? supports 8-bit progressive video monoch rome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) ? supports continuous mode or snapshot (a single frame) mode ? capability to automatically crop the image 3.32 true random numb er generator (rng) all stm32f2xxx products embed a true rng that delivers 32-bit random numbers produced by an integrated analog circuit. 3.33 gpios (general-purpose inputs/outputs) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current -capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o alternate function configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. to provide fast i/o handling, the gpios ar e on the fast ahb1 bus with a clock up to 120 mhz that leads to a maximum i/o toggling speed of 60 mhz.
functional overview stm32f20xxx 38/179 docid15818 rev 12 3.34 adcs (analog-to-digital converters) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted vo ltage is outside the programmed thresholds. the events generated by the timers tim1, tim2, tim3, tim4, tim5 and tim8 can be internally connected to the adc start trigger an d injection trigger, res pectively, to allow the application to synchronize a/d conversion and timers. 3.35 dac (digital-to-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the design stru cture is composed of integrated resistor strings and an amplifier in inverting configuration. this dual digital interface supports the following features: ? two dac converters: one for each output channel ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? input voltage reference v ref+ eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams. 3.36 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.8 and 3.6 v. the temperature sensor is internally connected to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. as the offset of the temperature sensor varies fr om chip to chip due to process variation, the internal temperature sensor is mainly suitab le for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used.
docid15818 rev 12 39/179 stm32f20xxx functional overview 178 3.37 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared wit h swdio and swclk, respectively, and a specific sequence on the tms pin is us ed to switch between jtag-dp and sw-dp. 3.38 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f20x through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instru ction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools.
pinouts and pin description stm32f20xxx 40/179 docid15818 rev 12 4 pinouts and pin description figure 10. stm32f20x lqfp64 pinout 1. the above figure shows the package top view. figure 11. stm32f20x wlcsp64+2 ballout 1. the above figure shows the package top view. 6"!4 0# /3#?). 0# /3#?/54 .234 0# 0# 0# 0# 633! 6$$! 0! 7 + 5 0 0! 0! 6$$ 633 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! 6$$ 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" 6#!0? 6$$ ,1&0 aic 0# 24#?!& 0( /3#?). 0( /3#?/54 6$$ 633 ! 0! 0! 0# 0" 0" 0" 0" 6$$ " 0! 0# 0" 0" "//4 0" 0# # 0! 6#!0? 0# 0$ )22/&& $ 0# 0! 0! 0# % 0! 0! & 0# 0# ' 0" 0# 0# 0! 0# ( 0" 0" 0" 0# * 0" 0" 6#!0? 0" 0" 0! 0! aic 6 "!4 633 0# 0# 633 6$$ 6$$ 0! .234 0( /3#?). 633 62%& 0# 0( /3#?/54 0# 0! 0! 2%'/&& 0! 633? 0" 0!
docid15818 rev 12 41/179 stm32f20xxx pinouts and pin description 178 figure 12. stm32f20x lqfp100 pinout 1. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. 2. the above figure shows the package top view. 0% 0% 0% 0% 0% 6"!4 0# /3#?). 0# /3#?/54 633 6$$ 0( /3#?). .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 7 + 5 0 0! 0! 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$ 2&5 6$$ 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! aie ,1&0 0# 24#?!& 0( /3#?/54
pinouts and pin description stm32f20xxx 42/179 docid15818 rev 12 figure 13. stm32f20x lqfp144 pinout 1. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. 2. the above figure shows the package top view. 2&5 6 $$ 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6 $$ 6 33 0' 0' 0' 0' 0' 0' 0$ 0$ 6 $$ 6 33 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 0% 6 $$ 0% 6 33 0% 0% 0! 0% 0! 6"!4 0! 0# 24#?!& 0! 0# /3#?). 0! 0# /3#?/54 0! 0& 0# 0& 0# 0& 0# 0& 0# 0& 6 $$ 0& 6 33 6 33 0' 6 $$ 0' 0& 0' 0& 0' 0& 0' 0& 0' 0& 0' 0( /3#?). 0$ 0( /3#?/54 0$ .234 6 $$ 0# 6 33 0# 0$ 0# 0$ 0# 0$ 6 33! 0$ 6 $$ 0$ 6 2%& 0$ 6 $$! 0" 0! 7 + 5 0 0" 0! 0" 0! 0" 0! 6 33 6 $$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6 $$ 0& 0& 0& 0' 0' 0% 0% 0% 6 33 6 $$ 0% 0% 0% 0% 0% 0% 0" 0" 6 #!0? 6 $$ ,1&0 aie 6 #!0?
docid15818 rev 12 43/179 stm32f20xxx pinouts and pin description 178 figure 14. stm32f20x lqfp176 pinout 1. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. 2. the above figure shows the package top view. 0$2?/. 6 $$ 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6 $$ 6 33 0' 0' 0' 0' 0' 0' 0$ 0$ 6 $$ 6 33 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0) 0) 0% 6 $$ 0% 6 33 0% 0% 0! 0% 0! 6"!4 0! 0) 24#?!& 0! 0# /3#?). 0! 0# /3#?/54 0! 0& 0# 0& 0# 0& 0# 0& 0# 0& 6 $$ 0& 6 33 6 33 0' 6 $$ 0' 0& 0' 0& 0' 0& 0' 0& 0' 0& 0' 0( /3#?). 0$ 0( /3#?/54 0$ .234 6 $$ 0# 6 33 0# 0$ 0# 0$ 0# 0$ 6 33! 0$ 6 $$ 0$ 6 2%& 0$ 6 $$! 0" 0! 7+50 0" 0! 0" 0! 0" 0! 6 33 6 $$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6 $$ 0& 0& 0& 0' 0' 0% 0% 0% 6 33 6 $$ 0% 0% 0% 0% 0% 0% 0" 0" 6 #!0? 6 $$ ,1&0 aie 6 #!0? 0) 0! 0! 6 $$ 6 33 0) 0) 0) 0( 0( 0( 0( 0( 0( 0( 0( 0) 0) 0( 0( 0( 6 $$ 6 33 0( 0# 24#?!& 0) 0) 0) 6 33 6 $$ 0( 0(
pinouts and pin description stm32f20xxx 44/179 docid15818 rev 12 figure 15. stm32f20x ufbga176 ballout 1. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. 2. the above figure shows the package top view. $ 3( 3( 3( 3( 3% 3% 3* 3* 3% 3% 3' 3& 3$ 3$ 3$ % 3( 3( 3( 3% 3% 3% 3*3*3*3* 3' 3' 3&3&3$ &9%$73,3,3, 5)8 9'' 9'' 9'' 9'' 3* 3' 3' 3, 3, 3$ ' 3& 7$03 3, 7$03 3, 3, %227 966 966 966 3' 3' 3' 3+ 3, 3$ ( 3& 26&b,1 3) 3, 3, 3+ 3+ 3, 3$ ) 3& 26&b287 966 9'' 3+ 966 966 966 966 966 966 9&$3b 3& 3$ * 3+ 26&b,1 966 9'' 3+ 966 966 966 966 966 966 9'' 3& 3& + 3+ 26&b287 3) 3) 3+ 966 966 966 966 966 966 9'' 3* 3& - 15673)3)3+ 966966966966966 9'' 9'' 3*3* . 3) 3) 3) 9'' 966 966 966 966 966 3+ 3* 3* 3* / 3) 3) 3) 5(*2)) 3+ 3+ 3' 3* 0 966$ 3& 3& 3& 3& 3% 3* 966 966 9&$3b 3+ 3+ 3+ 3' 3' 195()3$ 3$ :.83 3$ 3& 3) 3* 9'' 9'' 9'' 3( 3+ 3' 3' 3' 3 95() 3$ 3$ 3$ 3& 3) 3) 3( 3( 3( 3( 3% 3% 3' 3' 5 9''$ 3$ 3$ 3% 3% 3) 3) 3( 3( 3( 3( 3% 3% 3% 3% aic 966 table 7. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input/ output pin i/o structure ft 5 v tolerant i/o tta 3.3 v tolerant i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers
docid15818 rev 12 45/179 stm32f20xxx pinouts and pin description 178 table 8. stm32f20x pin and ball definitions pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176 - - 1 1 1 a2 pe2 i/o ft - traceclk, fsmc_a23, eth_mii_txd3, eventout - - - 2 2 2 a1 pe3 i/o ft - traced0,fsmc_a19, eventout - - - 3 3 3 b1 pe4 i/o ft - traced1,fsmc_a20, dcmi_d4, eventout - - - 4 4 4 b2 pe5 i/o ft - traced2, fsmc_a21, tim9_ch1, dcmi_d6, eventout - - - 5 5 5 b3 pe6 i/o ft - traced3, fsmc_a22, tim9_ch2, dcmi_d7, eventout - 1a96 6 6 c1 v bat s- - - ----7d2 pi8 i/oft (2)(3) eventout rtc_af2 2b87 7 8 d1 pc13 i/oft (2)(3) eventout rtc_af1 3b98 8 9 e1 pc14/osc32_in (pc14) i/o ft (2)(3) eventout osc32_in (4) 4c99 910f1 pc15-osc32_out (pc15) i/o ft (2)(3) eventout osc32_out (4) - - - - 11 d3 pi9 i/o ft - can1_rx,eventout - - - - - 12 e3 pi10 i/o ft - eth_mii_rx_er, eventout - - - - - 13 e4 pi11 i/o ft - otg_hs_ulpi_dir, eventout - ----14f2 v ss s- - ----15f3 v dd s- - ---1016e2 pf0 i/oft- fsmc_a0, i2c2_sda, eventout - ---1117h3 pf1 i/oft- fsmc_a1, i2c2_scl, eventout - ---1218h2 pf2 i/oft- fsmc_a2, i2c2_smba, eventout - ---1319j2 pf3 i/oft (4) fsmc_a3, eventout adc3_in9
pinouts and pin description stm32f20xxx 46/179 docid15818 rev 12 ---1420j3 pf4 i/oft (4) fsmc_a4, eventout adc3_in14 ---1521k3 pf5 i/oft (4) fsmc_a5, eventout adc3_in15 -h9101622g2 v ss s- - - - --111723g3 v dd s- - - - ---1824k2 pf6 i/oft (4) tim10_ch1, fsmc_niord, eventout adc3_in4 ---1925k1 pf7 i/oft (4) tim11_ch1,fsmc_nreg, eventout adc3_in5 ---2026l3 pf8 i/oft (4) tim13_ch1, fsmc_niowr, eventout adc3_in6 ---2127l2 pf9 i/oft (4) tim14_ch1, fsmc_cd, eventout adc3_in7 ---2228l1 pf10 i/oft (4) fsmc_intr, eventout adc3_in8 5e9122329g1 ph0/osc_in (ph0) i/o ft - eventout osc_in (4) 6f9132430h1 ph1/osc_out (ph1) i/o ft - eventout osc_out (4) 7 e8 14 25 31 j1 nrst i/o - - - 8g9152632m2 pc0 i/oft (4) otg_hs_ulpi_stp, eventout adc123_ in10 9f8162733m3 pc1 i/oft (4) eth_mdc, eventout adc123_ in11 10 d7 17 28 34 m4 pc2 i/o ft (4) spi2_miso, otg_hs_ulpi_dir, eth_mii_txd2, eventout adc123_ in12 11 g8 18 29 35 m5 pc3 i/o ft (4) spi2_mosi, i2s2_sd, otg_hs_ulpi_nxt, eth_mii_tx_clk, eventout adc123_ in13 - - 19 30 36 - v dd s- - - - 12 - 20 31 37 m1 v ssa s- - - - -----n1 v ref- s- - - - -f7213238p1 v ref+ s- - - - table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
docid15818 rev 12 47/179 stm32f20xxx pinouts and pin description 178 13 - 22 33 39 r1 v dda s- - - - 14 e7 23 34 40 n3 pa0-wkup (pa0) i/o ft (4)(5) usart2_cts, uart4_tx, eth_mii_crs, tim2_ch1_etr, tim5_ch1, tim8_etr, eventout adc123_in0, wkup 15 h8 24 35 41 n2 pa1 i/o ft (4) usart2_rts, uart4_rx, eth_rmii_ref_clk, eth_mii_rx_clk, tim5_ch2, tim2_ch2, eventout adc123_in1 16 j9 25 36 42 p2 pa2 i/o ft (4) usart2_tx,tim5_ch3, tim9_ch1, tim2_ch3, eth_mdio, eventout adc123_in2 - - - - 43 f4 ph2 i/o ft - eth_mii_crs, eventout - - - - - 44 g4 ph3 i/o ft - eth_mii_col, eventout - ----45h4 ph4 i/oft- i2c2_scl, otg_hs_ulpi_nxt, eventout - - - - - 46 j4 ph5 i/o ft - i2c2_sda, eventout - 17 g7 26 37 47 r2 pa3 i/o ft (4) usart2_rx, tim5_ch4, tim9_ch2, tim2_ch4, otg_hs_ulpi_d0, eth_mii_col, eventout adc123_in3 18 f1 27 38 48 - v ss s- - - - h7 l4 regoff i/o - - - - 19 e1 28 39 49 k4 v dd s- - - - 20 j8 29 40 50 n4 pa4 i/o tta (4) spi1_nss, spi3_nss, usart2_ck, dcmi_hsync, otg_hs_sof, i2s3_ws, eventout adc12_in4, dac_out1 21 h6 30 41 51 p4 pa5 i/o tta (4) spi1_sck, otg_hs_ulpi_ck, tim2_ch1_etr, tim8_ch1n, eventout adc12_in5, dac_out2 table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f20xxx 48/179 docid15818 rev 12 22 h5 31 42 52 p3 pa6 i/o ft (4) spi1_miso, ti m8_bkin, tim13_ch1, dcmi_pixclk, tim3_ch1, tim1_bkin, eventout adc12_in6 23 j7 32 43 53 r3 pa7 i/o ft (4) spi1_mosi, tim8_ch1n, tim14_ch1, tim3_ch2, eth_mii_rx_dv, tim1_ch1n, eth_rmii_crs_dv, eventout adc12_in7 24 h4 33 44 54 n5 pc4 i/o ft (4) eth_rmii_rxd0, eth_mii_rxd0, eventout adc12_in14 25 g3 34 45 55 p5 pc5 i/o ft (4) eth_rmii_rxd1, eth_mii_rxd1, eventout adc12_in15 26 j6 35 46 56 r5 pb0 i/o ft (4) tim3_ch3, tim8_ch2n, otg_hs_ulpi_d1, eth_mii_rxd2, tim1_ch2n, eventout adc12_in8 27 j5 36 47 57 r4 pb1 i/o ft (4) tim3_ch4, tim8_ch3n, otg_hs_ulpi_d2, eth_mii_rxd3, tim1_ch3n, eventout adc12_in9 28 j4 37 48 58 m6 pb2/boot1 (pb2) i/o ft - eventout - - - - 49 59 r6 pf11 i/o ft - dcmi_d12, eventout - - - - 50 60 p6 pf12 i/o ft - fsmc_a6, eventout - ---5161m8 v ss s- - ---5262n8 v dd s- - - - - 53 63 n6 pf13 i/o ft - fsmc_a7, eventout - - - - 54 64 r7 pf14 i/o ft - fsmc_a8, eventout - - - - 55 65 p7 pf15 i/o ft - fsmc_a9, eventout - - - - 56 66 n7 pg0 i/o ft - fsmc_a10, eventout - - - - 57 67 m7 pg1 i/o ft - fsmc_a11, eventout - table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
docid15818 rev 12 49/179 stm32f20xxx pinouts and pin description 178 - - 38 58 68 r8 pe7 i/o ft - fsmc_d4,tim1_etr, eventout - - - 39 59 69 p8 pe8 i/o ft - fsmc_d5,tim1_ch1n, eventout - - - 40 60 70 p9 pe9 i/o ft - fsmc_d6,tim1_ch1, eventout - ---6171m9 v ss s- - ---6272n9 v dd s- - - - 41 63 73 r9 pe10 i/o ft - fsmc_d7,tim1_ch2n, eventout - - - 42 64 74 p10 pe11 i/o ft - fsmc_d8,tim1_ch2, eventout - - - 43 65 75 r10 pe12 i/o ft - fsmc_d9,tim1_ch3n, eventout - - - 44 66 76 n11 pe13 i/o ft - fsmc_d10,tim1_ch3, eventout - - - 45 67 77 p11 pe14 i/o ft - fsmc_d11,tim1_ch4, eventout - - - 46 68 78 r11 pe15 i/o ft - fsmc_d12,tim1_bkin, eventout - 29 h3 47 69 79 r12 pb10 i/o ft - spi2_sck, i2s2_sck, i2c2_scl,usart3_tx,ot g_hs_ulpi_d3,eth_mii_r x_er,tim2_ch3, eventout - 30 j2 48 70 80 r13 pb11 i/o ft - i2c2_sda, usart3_rx, otg_hs_ulpi_d4, eth_rmii_tx_en, eth_mii_tx_en, tim2_ch4, eventout - 31 j3 49 71 81 m10 v cap_1 s- - 32 - 50 72 82 n10 v dd s- - ----83m11 ph6 i/oft- i2c2_smba, tim12_ch1, eth_mii_rxd2, eventout - table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f20xxx 50/179 docid15818 rev 12 - - - - 84 n12 ph7 i/o ft - i2c3_scl, eth_mii_rxd3, eventout - ----85m12 ph8 i/oft- i2c3_sda, dcmi_hsync, eventout - ----86m13 ph9 i/oft- i2c3_smba, tim12_ch2, dcmi_d0, eventout - - - - - 87 l13 ph10 i/o ft - tim5_ch1, dcmi_d1, eventout - - - - - 88 l12 ph11 i/o ft - tim5_ch2, dcmi_d2, eventout - ----89k12 ph12 i/oft- tim5_ch3, dcmi_d3, eventout - ----90h12 v ss s- - ----91j12 v dd s- - 33 j1 51 73 92 p12 pb12 i/o ft - spi2_nss, i2s2_ws, i2c2_smba, usart3_ck, tim1_bkin, can2_rx, otg_hs_ulpi_d5, eth_rmii_txd0, eth_mii_txd0, otg_hs_id, eventout - 34 h2 52 74 93 p13 pb13 i/o ft - spi2_sck, i2s2_sck, usart3_cts, tim1_ch1n, can2_tx, otg_hs_ulpi_d6, eth_rmii_txd1, eth_mii_txd1, eventout otg_hs_ vbus 35 h1 53 75 94 r14 pb14 i/o ft - spi2_miso, tim1_ch2n, tim12_ch1, otg_hs_dm usart3_rts, tim8_ch2n, eventout - 36 g1 54 76 95 r15 pb15 i/o ft - spi2_mosi, i2s2_sd, tim1_ch3n, tim8_ch3n, tim12_ch2, otg_hs_dp, rtc_50hz , eventout - - - 55 77 96 p15 pd8 i/o ft - fsmc_d13, usart3_tx, eventout - table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
docid15818 rev 12 51/179 stm32f20xxx pinouts and pin description 178 - - 56 78 97 p14 pd9 i/o ft - fsmc_d14, usart3_rx, eventout - - - 57 79 98 n15 pd10 i/o ft - fsmc_d15, usart3_ck, eventout - - - 58 80 99 n14 pd11 i/o ft - fsmc_a16,usart3_cts, eventout - - - 59 81 100 n13 pd12 i/o ft - fsmc_a17,tim4_ch1, usart3_rts, eventout - - - 60 82 101 m15 pd13 i/o ft - fsmc_a18,tim4_ch2, eventout - ---83102- v ss s- - ---84103j13 v dd s- - - - 61 85 104 m14 pd14 i/o ft - fsmc_d0,tim4_ch3, eventout - - - 62 86 105 l14 pd15 i/o ft - fsmc_d1,tim4_ch4, eventout - - - - 87 106 l15 pg2 i/o ft - fsmc_a12, eventout - - - - 88 107 k15 pg3 i/o ft - fsmc_a13, eventout - - - - 89 108 k14 pg4 i/o ft - fsmc_a14, eventout - - - - 90 109 k13 pg5 i/o ft - fsmc_a15, eventout - - - - 91 110 j15 pg6 i/o ft - fsmc_int2, eventout - - - - 92 111 j14 pg7 i/o ft - fsmc_int3 ,usart6_ck, eventout - - - - 93 112 h14 pg8 i/o ft - usart6_rts, eth_pps_out, eventout - ---94113g12 v ss s- - ---95114h13 v dd s- - 37 g2 63 96 115 h15 pc6 i/o ft - i2s2_mck, tim8_ch1, sdio_d6, usart6_tx, dcmi_d0, tim3_ch1, eventout - table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f20xxx 52/179 docid15818 rev 12 38 f2 64 97 116 g15 pc7 i/o ft - i2s3_mck, tim8_ch2, sdio_d7, usart6_rx, dcmi_d1, tim3_ch2, eventout - 39 f3 65 98 117 g14 pc8 i/o ft - tim8_ch3,sdio_d0, tim3_ch3, usart6_ck, dcmi_d2, eventout - 40 d1 66 99 118 f14 pc9 i/o ft - i2s2_ckin, i2s3_ckin, mco2, tim8_ch4, sdio_d1, i2c3_sda, dcmi_d3, tim3_ch4, eventout - 41 e2 67 100 119 f15 pa8 i/o ft - mco1, usart1_ck, tim1_ch1, i2c3_scl, otg_fs_sof, eventout - 42 e3 68 101 120 e15 pa9 i/o ft - usart1_tx, tim1_ch2, i2c3_smba, dcmi_d0, eventout otg_fs_ vbus 43 d3 69 102 121 d15 pa10 i/o ft - usart1_rx, tim1_ch3, otg_fs_id,dcmi_d1, eventout - 44 d2 70 103 122 c15 pa11 i/o ft - usart1_cts, can1_rx, tim1_ch4,otg_fs_dm, eventout - 45 c1 71 104 123 b15 pa12 i/o ft - usart1_rts, can1_tx, tim1_etr, otg_fs_dp, eventout - 46 b2 72 105 124 a15 pa13 (jtms-swdio) i/o ft - jtms-swdio, eventout - 47 c2 73 106 125 f13 v cap_2 s- - - b1 74 107 126 f12 v ss s- - 48 a8 75 108 127 g13 v dd s- - - - - - 128 e12 ph13 i/o ft - tim8_ch1n, can1_tx, eventout - - - - - 129 e13 ph14 i/o ft - tim8_ch2n, dcmi_d4, eventout - table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
docid15818 rev 12 53/179 stm32f20xxx pinouts and pin description 178 - - - - 130 d13 ph15 i/o ft - tim8_ch3n, dcmi_d11, eventout - ----131e14 pi0 i/oft- tim5_ch4, spi2_nss, i2s2_ws, dcmi_d13, eventout - ----132d14 pi1 i/oft- spi2_sck, i2s2_sck, dcmi_d8, eventout - ----133c14 pi2 i/oft- tim8_ch4 ,spi2_miso, dcmi_d9, eventout - ----134c13 pi3 i/oft- tim8_etr, spi2_mosi, i2s2_sd, dcmi_d10, eventout - ----135d9 v ss s- - ----136c9 v dd s- - 49 a1 76 109 137 a14 pa14 (jtck-swclk) i/o ft - jtck-swclk, eventout - 50 a2 77 110 138 a13 pa15 (jtdi) i/o ft - jtdi, spi3_nss, i2s3_ws,tim2_ch1_etr, spi1_nss, eventout - 51 b3 78 111 139 b14 pc10 i/o ft - spi3_sck, i2s3_sck, uart4_tx, sdio_d2, dcmi_d8, usart3_tx, eventout - 52 c3 79 112 140 b13 pc11 i/o ft - uart4_rx, spi3_miso, sdio_d3, dcmi_d4,usart3_rx, eventout - 53 a3 80 113 141 a12 pc12 i/o ft - uart5_tx, sdio_ck, dcmi_d9, spi3_mosi, i2s3_sd, usart3_ck, eventout - --81114142b12 pd0 i/oft- fsmc_d2,can1_rx, eventout - - - 82 115 143 c12 pd1 i/o ft - fsmc_d3, can1_tx, eventout - table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f20xxx 54/179 docid15818 rev 12 54 c7 83 116 144 d12 pd2 i/o ft - tim3_etr,uart5_rx, sdio_cmd, dcmi_d11, eventout - - - 84 117 145 d11 pd3 i/o ft - fsmc_clk,usart2_cts, eventout - - - 85 118 146 d10 pd4 i/o ft - fsmc_noe, usart2_rts, eventout - - - 86 119 147 c11 pd5 i/o ft - fsmc_nwe,usart2_tx, eventout - - - - 120 148 d8 v ss s- - - - - 121 149 c8 v dd s- - - - 87 122 150 b11 pd6 i/o ft - fsmc_nwait, usart2_rx, eventout - - - 88 123 151 a11 pd7 i/o ft - usart2_ck,fsmc_ne1, fsmc_nce2, eventout - - - - 124 152 c10 pg9 i/o ft - usart6_rx, fsmc_ne2,fsmc_nce3, eventout - - - - 125 153 b10 pg10 i/o ft - fsmc_nce4_1, fsmc_ne3, eventout - - - - 126 154 b9 pg11 i/o ft - fsmc_nce4_2, eth_mii_tx_en , eth _rmii_tx_en, eventout - - - - 127 155 b8 pg12 i/o ft - fsmc_ne4, usart6_rts, eventout - - - - 128 156 a8 pg13 i/o ft - fsmc_a24, usart6_cts, eth_mii_txd0, eth_rmii_txd0, eventout - - - - 129 157 a7 pg14 i/o ft - fsmc_a25, usart6_tx, eth_mii_txd1, eth_rmii_txd1, eventout - - - - 130 158 d7 v ss s- - table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
docid15818 rev 12 55/179 stm32f20xxx pinouts and pin description 178 - - - 131 159 c7 v dd s- - -- - - - - 132 160 b7 pg15 i/o ft - usart6_cts, dcmi_d13, eventout - 55 a4 89 133 161 a10 pb3 (jtdo/traceswo) i/o ft - jtdo/ traceswo, spi3_sck, i2s3_sck, tim2_ch2, spi1_sck, eventout - 56 b4 90 134 162 a9 pb4 i/o ft - njtrst, spi3_miso, tim3_ch1, spi1_miso, eventout - 57 a5 91 135 163 a6 pb5 i/o ft - i2c1_smba, can2_rx, otg_hs_ulpi_d7, eth_pps_out, tim3_ch2, spi1_mosi, spi3_mosi, dcmi_d10, i2s3_sd, eventout - 58 b5 92 136 164 b6 pb6 i/o ft - i2c1_scl,, tim4_ch1, can2_tx, dcmi_d5,usart1_tx, eventout - 59 a6 93 137 165 b5 pb7 i/o ft - i2c1_sda, fsmc_nl (6) , dcmi_vsync, usart1_rx, tim4_ch2, eventout - 60 b6 94 138 166 d6 boot0 i b - v pp 61 b7 95 139 167 a5 pb8 i/o ft - tim4_ch3,sdio_d4, tim10_ch1, dcmi_d6, eth_mii_txd3, i2c1_scl, can1_rx, eventout - 62 a7 96 140 168 b4 pb9 i/o ft - spi2_nss, i2s2_ws , tim4_ch4, tim11_ch1, sdio_d5, dcmi_d7, i2c1_sda, can1_tx, eventout - - - 97 141 169 a4 pe0 i/o ft - tim4_etr, fsmc_nbl0, dcmi_d2, eventout - table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f20xxx 56/179 docid15818 rev 12 - - 98 142 170 a3 pe1 i/o ft - fsmc_nbl1, dcmi_d3, eventout - -----d5 v ss s- - 63 d8 - - - - v ss s- - - - 99 143 171 c6 rfu (7) - 64 d9 100 144 172 c5 v dd s- - ----173d4 pi4 i/oft- tim8_bkin, dcmi_d5, eventout - ----174c4 pi5 i/oft- tim8_ch1, dcmi_vsync, eventout - ----175c3 pi6 i/oft- tim8_ch2, dcmi_d6, eventout - ----176c2 pi7 i/oft- tim8_ch3, dcmi_d7, eventout - - c8 - - - - irroff i/o - - 1. function availability depends on the chosen device. 2. pc13, pc14, pc15 and pi8 are supplied through the power switch . since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: the speed shoul d not exceed 2 mhz with a maximum load of 30 pf and these i/os must not be used as a current source (e.g. to drive an led). 3. main function after the first backup domain power-up. late r on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main rese t). for details on how to manage these i/os, refer to the rtc register description sections in the stm32f20x and stm32f 21x reference manual, available from the stmicroelectronics website: www.st.com. 4. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc14, pc15, ph0 and ph1). 5. if the device is delivered in an ufbga176 package and if the regoff pin is set to v dd (regulator off), then pa0 is used as an internal reset (active low). 6. fsmc_nl pin is also named fsmc_nadv on memory devices. 7. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. table 8. stm32f20x pin and ball definitions (continued) pins pin name (function after reset) (1) pin type i/o structure note alternate functions additional functions lqfp64 wlcsp64+2 lqfp100 lqfp144 lqfp176 ufbga176 table 9. fsmc pin definition pins fsmc lqfp100 cf nor/psram/s ram nor/psram mux nand 16 bit pe2 - a23 a23 - yes pe3 - a19 a19 - yes
docid15818 rev 12 57/179 stm32f20xxx pinouts and pin description 178 pe4 - a20 a20 - yes pe5 - a21 a21 - yes pe6 - a22 a22 - yes pf0 a0 a0 - - - pf1 a1 a1 - - - pf2 a2 a2 - - - pf3 a3 a3 - - - pf4 a4 a4 - - - pf5 a5 a5 - - - pf6 niord - - - - pf7 nreg - - - - pf8 niowr - - - - pf9 cd - - - - pf10 intr - - - - pf12 a6 a6 - - - pf13 a7 a7 - - - pf14 a8 a8 - - - pf15 a9 a9 - - - pg0 a10 a10 - - - pg1 - a11 - - - pe7 d4 d4 da4 d4 yes pe8 d5 d5 da5 d5 yes pe9 d6 d6 da6 d6 yes pe10 d7 d7 da7 d7 yes pe11 d8 d8 da8 d8 yes pe12 d9 d9 da9 d9 yes pe13 d10 d10 da10 d10 yes pe14 d11 d11 da11 d11 yes pe15 d12 d12 da12 d12 yes pd8 d13 d13 da13 d13 yes pd9 d14 d14 da14 d14 yes pd10 d15 d15 da15 d15 yes pd11 - a16 a16 cle yes table 9. fsmc pin definition (continued) pins fsmc lqfp100 cf nor/psram/s ram nor/psram mux nand 16 bit
pinouts and pin description stm32f20xxx 58/179 docid15818 rev 12 pd12 - a17 a17 ale yes pd13 - a18 a18 yes pd14 d0 d0 da0 d0 yes pd15 d1 d1 da1 d1 yes pg2 - a12 - - - pg3 - a13 - - - pg4 - a14 - - - pg5 - a15 - - - pg6 - - - int2 - pg7 - - - int3 - pd0 d2 d2 da2 d2 yes pd1 d3 d3 da3 d3 yes pd3 clk clk - yes pd4 noe noe noe noe yes pd5 nwe nwe nwe nwe yes pd6 nwait nwait nwait nwait yes pd7 ne1 ne1 nce2 yes pg9 ne2 ne2 nce3 - pg10 nce4_1 ne3 ne3 - - pg11 nce4_2 - - - - pg12 - ne4 ne4 - - pg13 - a24 a24 - - pg14 - a25 a25 - - pb7 - nadv nadv - yes pe0 - nbl0 nbl0 - yes pe1 - nbl1 nbl1 - yes table 9. fsmc pin definition (continued) pins fsmc lqfp100 cf nor/psram/s ram nor/psram mux nand 16 bit
stm32f20xxx pinouts and pin description docid15818 rev 12 59/179 table 10. alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi port a pa0-wkup - tim2_ch1_etr tim 5_ch1 tim8_etr - - usar t2_cts uart4_tx - - eth_mii_crs - - - eventout pa1 - tim2_ch2 tim5_ch2 - - - usart2_rts uart4_rx - - eth_mii _rx_clk eth_rmii _ref_clk ---eventout pa2 - tim2_ch3 tim5_ch3 tim9_ch1 - - usart2_tx - - - eth_mdio - - - eventout pa3 - tim2_ch4 tim5_ch4 tim9_ch2 - - usart2_r x - - otg_hs_ulpi_d0 eth _mii_col - - - eventout pa4 - - - - - spi1_nss spi3_nss i2s3_ws usart2_ck - - - otg_hs_sof dcmi_hsync - eventout pa5 - tim2_ch1_etr - tim8_ch1n - spi1_sck - - - - otg_hs_ulpi_c k - - - - eventout pa6 - tim1_bkin tim3_ch1 tim8_bkin - spi1_miso - - - tim13_ch1 - - - dcmi_pixck - eventout pa7 - tim1_ch1n tim3_ch2 tim8_ch1n - spi1_mosi - - - tim14_ch1 - eth_mii _rx_dv eth_rmii _crs_dv ---eventout pa8 mco1 tim1_ch1 - - i2c3_scl - - usart1_ck - - otg_fs_sof - - - - eventout pa9 - tim1_ch2 - - i2c3_smba - - usart1_tx - - - - dcmi_d0 - eventout pa10 - tim1_ch3 - - - - - usart1_rx - - otg_fs_id - - dcmi_d1 - eventout pa11 - tim1_ch4 - - - - - usart1_cts - can1_rx otg_fs_dm - - - - eventout pa12 - tim1_etr - - - - - usart1_rts - can1_tx otg_fs_dp - - - - eventout pa13 jtms- swdio - - - - - - - - - - - - - - eventout pa14 jtck- swclk - - - - - - - - - - - - - - eventout pa15 jtdi tim 2_ch1 tim 2_etr - - - spi1_nss spi3_nss i2s3_ws - - - - - - - - eventout
pinouts and pin description stm32f20xxx 60/179 docid15818 rev 12 port b pb0 - tim1_ch2n tim3_ch3 tim8_ch2n - - - - - - ot g_hs_ulpi_d1 eth _mii_rxd2 - - - eventout pb1 - tim1_ch3n tim3_ch4 tim8_ch3n - - - - - - ot g_hs_ulpi_d2 eth _mii_rxd3 - - - eventout pb2 - - - - - - - - - - - - - - - eventout pb3 jtdo/ traceswo tim2_ch2 - - - spi1_sck spi3_sck i2s3_sck - - - - - - - - eventout pb4 jtrst - tim3_ch1 - - spi1_miso spi3_miso - - - - - - - - eventout pb5 - - tim3_ch2 - i2c1_smba spi1_mosi spi3_mosi i2s3_sd - - can2_rx otg_hs_ulpi_d7 eth _pps_out - dcmi_d10 - eventout pb6 - - tim4_ch1 - i2c1_scl - - usart1_tx - can2_tx - - - dcmi_d5 - eventout pb7 - - tim4_ch2 - i2c1_sda - - usart1_rx - - - - fsmc_nl dcmi_vsync - eventout pb8 - - tim4_ch3 tim10_ch1 i2c1_scl - - - - can1_rx - eth _mii_txd3 sdio_d4 dcmi_d6 - eventout pb9 - - tim4_ch4 tim11_ch1 i2c1_sda spi2_nss i2s2_ws - - - can1_tx - - sdio_d5 dcmi_d7 - eventout pb10 - tim2_ch3 - - i2c2_scl spi2_sck i2s2_sck - usart3_tx - - otg_hs_ulpi_d3 eth_ mii_rx_er - - - eventout pb11 - tim2_ch4 - - i2c2_sda - - usart3_rx - - otg_hs_ulpi_d4 eth _mii_tx_en eth _rmii_tx_en ---eventout pb12 - tim1_bkin - - i2c2_smba spi2_nss i2s2_ws - usart3_ck - can2_rx otg_hs_ulpi_d5 eth _mii_txd0 eth _rmii_txd0 otg_hs_id - - eventout pb13 - tim1_ch1n - - - spi2_sck i2s2_sck - usart3_cts - can2_tx otg_hs_ulpi_d6 eth _mii_txd1 eth _rmii_txd1 ---eventout pb14 - tim1_ch2n - tim8_ch2n - spi2_miso - usart3_rts - tim12_ch1 - - otg_hs_dm - - eventout pb15 rtc_50hz tim1_ch3n - tim8_ch3n - spi2_mosi i2s2_sd - - - tim12_ch2 - - otg_hs_dp - - eventout table 10. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi
stm32f20xxx pinouts and pin description docid15818 rev 12 61/179 port c pc0 - - - - - - - - - - otg_hs_ulpi_ stp - - - - eventout pc1 - - - - - - - - - - - eth_mdc - - - eventout pc2 - - - - - spi2_miso - - - - otg_hs_ulpi_ dir eth _mii_txd2 - - - eventout pc3 - - - - - spi2_mosi - - - - otg_hs_ulpi_ nxt eth _mii_tx_clk ---eventout pc4 - - - - - - - - - - - eth_mii_rxd0 eth_rmii_rxd0 ---eventout pc5 - - - - - - - - - - - eth _mii_rxd1 eth _rmii_rxd1 ---eventout pc6 - - tim3_ch1 tim8_ch1 - i2s2_mck - - usart6_tx - - - sdio_d6 dcmi_d0 - eventout pc7 - - tim3_ch2 tim8_ch2 - - i2s3_mck - usart6_rx - - - sdio_d7 dcmi_d1 - eventout pc8 - - tim3_ch3 tim8_ch3 - - - - usart6_ck - - - sdio_d0 dcmi_d2 - eventout pc9 mco2 - tim3_ch4 tim8_ch4 i2c3_sda i2s2_cki n i2s3_ckin - - - - - sdio_d1 dcmi_d3 - eventout pc10 - - - - - - spi3_sck i2s3_sck usart3_tx uart4_tx - - - sdio_d2 dcmi_d8 - eventout pc11 - - - - - - spi3_miso usart3_rx uart4_rx - - - sdio_d3 dcmi_d4 - eventout pc12 - - - - - - spi3_mosi i2s3_sd usart3_ck uart5_tx - - - sdio_ck dcmi_d9 - eventout pc13 - - - - - - - - - - - - - - - eventout pc14- osc32_in -- - - - - - - - - - - - --eventout pc15- osc32_ou t -- - - - - - - - - - - - --eventout table 10. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi
pinouts and pin description stm32f20xxx 62/179 docid15818 rev 12 port d pd0 - - - - - - - - - can1_rx - - fsmc_d2 - - eventout pd1 - - - - - - - - - can1_tx - - fsmc_d3 - - eventout pd2 - - tim3_etr - - - - - uart5_rx - - - sdio_cmd dcmi_d11 - eventout pd3 - - - - - - - usart2_cts - - - - fsmc_clk - - eventout pd4 - - - - - - - usart2_rts - - - - fsmc_noe - - eventout pd5 - - - - - - - usart2_tx - - - - fsmc_nwe - - eventout pd6 - - - - - - - usart2_rx - - - - fsmc_nwait - - eventout pd7 - - - - - - - usart2_ck - - - - fsmc_ne1/ fsmc_nce2 - - eventout pd8 - - - - - - - usart3_tx - - - - fsmc_d13 - - eventout pd9 - - - - - - - usart3_rx - - - - fsmc_d14 - - eventout pd10 - - - - - - - usart3_ck - - - - fsmc_d15 - - eventout pd11 - - - - - - - usart3_cts - - - - fsmc_a16 - - eventout pd12 - - tim4_ch1 - - - - usart3_rts - - - - fsmc_a17 - - eventout pd13 - - tim4_ch2 - - - - - - - - - fsmc_a18 - - eventout pd14 - - tim4_ch3 - - - - - - - - - fsmc_d0 - - eventout pd15 - - tim4_ch4 - - - - - - - - - fsmc_d1 - - eventout port e pe0 - - tim4_etr - - - - - - - - - fsmc_nbl0 dcmi_d2 - eventout pe1 - - - - - - - - - - - - fsmc_nbl1 dcmi_d3 - eventout pe2 traceclk - - - - - - - - - - eth _mii_txd3 fsmc_a23 - - eventout pe3 traced0 - - - - - - - - - - - fsmc_a19 - - eventout pe4 traced1 - - - - - - - - - - - fsmc_a20 dcmi_d4 - eventout pe5 traced2 - - tim9_ch1 - - - - - - - - fsmc_a21 dcmi_d6 - eventout pe6 traced3 - - tim9_ch2 - - - - - - - - fsmc_a22 dcmi_d7 - eventout pe7 - tim1_etr - - - - - - - - - - fsmc_d4 - - eventout pe8 - tim1_ch1n - - - - - - - - - - fsmc_d5 - - eventout pe9 - tim1_ch1 - - - - - - - - - - fsmc_d6 - - eventout pe10 - tim1_ch2n - - - - - - - - - - fsmc_d7 - - eventout pe11 - tim1_ch2 - - - - - - - - - - fsmc_d8 - - eventout pe12 - tim1_ch3n - - - - - - - - - - fsmc_d9 - - eventout pe13 - tim1_ch3 - - - - - - - - - - fsmc_d10 - - eventout pe14 - tim1_ch4 - - - - - - - - - - fsmc_d11 - - eventout pe15 - tim1_bkin - - - - - - - - - - fsmc_d12 - - eventout table 10. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi
stm32f20xxx pinouts and pin description docid15818 rev 12 63/179 port f pf0 - - - - i2c2_sda - - - - - - - fsmc_a0 - - eventout pf1 - - - - i2c2_scl - - - - - - fsmc_a1 - - eventout pf2 - - - - i2c2_smba - - - - - - - fsmc_a2 - - eventout pf3 - - - - - - - - - - - - fsmc_a3 - - eventout pf4 - - - - - - - - - - - - fsmc_a4 - - eventout pf5 - - - - - - - - - - - - fsmc_a5 - - eventout pf6 - - - tim10_ch1 - - - - - - - - fsmc_niord - - eventout pf7 - - - tim11_ch1 - - - - - - - - fsmc_nreg - - eventout pf8 - - - - - - - - - tim13_ch1 - - fsmc_niowr - - eventout pf9 - - - - - - - - - tim14_ch1 - - fsmc_cd - - eventout pf10 - - - - - - - - - - - - fsmc_intr - - eventout pf11 - - - - - - - - - - - - dcmi_d12 - eventout pf12 - - - - - - - - - - - - fsmc_a6 - - eventout pf13 - - - - - - - - - - - - fsmc_a7 - - eventout pf14 - - - - - - - - - - - - fsmc_a8 - - eventout pf15 - - - - - - - - - - - - fsmc_a9 - - eventout port g pg0 - - - - - - - - - - - - fsmc_a10 - - eventout pg1 - - - - - - - - - - - - fsmc_a11 - - eventout pg2 - - - - - - - - - - - - fsmc_a12 - - eventout pg3 - - - - - - - - - - - - fsmc_a13 - - eventout pg4 - - - - - - - - - - - - fsmc_a14 - - eventout pg5 - - - - - - - - - - - - fsmc_a15 - - eventout pg6 - - - - - - - - - - - - fsmc_int2 - - eventout pg7 - - - - - - - - usart6_ck - - - fsmc_int3 - - eventout pg8 - - - - - - - - usart6_rts - - eth _pps_out - - - eventout pg9 - - - - - - - - usart6_rx - - - fsmc_ne2/ fsmc_nce3 - - eventout pg10 - - - - - - - - - - - - fsmc_nce4_1/ fsmc_ne3 - - eventout pg11 - - - - - - - - - - - eth _mii_tx_en eth _rmii_tx_en fsmc_nce4_2 - - eventout pg12 - - - - - - - - usart6_rts - - - fsmc_ne4 - - eventout pg13 - - - - - - - - uart6_cts - - eth _mii_txd0 eth _rmii_txd0 fsmc_a24 - - eventout pg14 - - - - - - - - usart6_tx - - eth _mii_txd1 eth _rmii_txd1 fsmc_a25 - - eventout pg15 - - - - - - - - usart6_cts - - - - dcmi_d13 - eventout table 10. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi
pinouts and pin description stm32f20xxx 64/179 docid15818 rev 12 port h ph0 - osc_in -- - - - - - - - - - - - --eventout ph1 - osc_out - - - - - - - - - - - - eventout ph2 - - - - - - - - eth _mii_crs - - - eventout ph3 - - - - - - - - eth _mii_col - - - eventout ph4 - - i2c2_scl - - - - - otg_hs_ulpi_n xt - - - - eventout ph5 - - i2c2_sda - - - - - - - - - - eventout ph6 - - i2c2_smba - - - - tim12_ch1 - eth _mii_rxd2 - - - eventout ph7 - - i2c3_scl - - - - - - eth _mii_rxd3 - - - eventout ph8 - - i2c3_sda - - - - - - - - dcmi_hsync - eventout ph9 - - i2c3_smba - - - - tim12_ch2 - - - dcmi_d0 - eventout ph10 - - tim5_ch1 - - - - - - - - dcmi_d1 - eventout ph11 - - tim5_ch2 - - - - - - - - dcmi_d2 - eventout ph12 - - tim5_ch3 - - - - - - - - dcmi_d3 - eventout ph13 - - tim8_ch1n - - - - can1_tx - - - - - eventout ph14 - - tim8_ch2n - - - - - - - - dcmi_d4 - eventout ph15 - - tim8_ch3n - - - - - - - - dcmi_d11 - eventout port i pi0 - - tim5_ch4 spi2_nss i2s2_ws - - - - - - - dcmi_d13 - eventout pi1 - - spi2_sck i2s2_sck - - - - - - - dcmi_d8 - eventout pi2 - - tim8_ch4 spi2_miso - - - - - - - dcmi_d9 - eventout pi3 - - tim8_etr spi2_mosi i2s2_sd - - - - - - - dcmi_d10 - eventout pi4 - - tim8_bkin - - - - - - - - dcmi_d5 - eventout pi5 - - tim8_ch1 - - - - - - - - dcmi_vsync - eventout pi6 - - tim8_ch2 - - - - - - - - dcmi_d6 - eventout pi7 - - tim8_ch3 - - - - - - - - dcmi_d7 - eventout pi8 - - - - - - - - - - - - eventout pi9 - - - - - - can1_rx - - - - - eventout pi10 - - - - - - - - eth _mii_rx_er - - - eventout pi11 - - - - - - - otg_hs_ulpi_ dir - - - - eventout table 10. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi
docid15818 rev 12 65/179 stm32f20xxx memory mapping 178 5 memory mapping the memory map is shown in figure 16 .
memory mapping stm32f20xxx 66/179 docid15818 rev 12 figure 16. memory map -byte block #ortex -gs internal peripherals -byte block .otused -byte block &3-#registers -byte block &3-#bank bank -byte block &3-#bank bank -byte block 0eripherals -byte block 32!- x x&&&&&&& x x&&&&&&& x x&&&&&&& x x&&&&&&& x x&&&&&&& x! x"&&&&&&& x# x$&&&&&&& x% x&&&&&&&& -byte block #ode &lash x x&&&&&&& x&&& x&&&!& x&&&# x&&&# x x&&&&& x# x&&&&&& x x&&&&& 3ystemmemory/40 2eserved 2eserved !liasedto&lashsystem memoryor32!-depending onthe"//4pins 32!-+"aliased bybit banding 2eserved x x"&&& x# x&&&& x x&&&&&&& 4)- 4)- x x&& 4)- 4)- 4)- 4)- 2eserved x x&& x x"&& x# x&&& x x&& x x&& x x&& 24#"+0registers x x"&& 77$' x# x&&& )7$' x x&& 2eserved x x&& 30))3 x x"&& 30))3 x# x&&& 2eserved x x&& 53!24 x x&& x x"&& 53!24 5!24 x# x&&& 5!24 x x&& )# x x&& )# x x"&& 2eserved x# x&&& x x&& 072 x x&& $!#$!# x x&&&& 4)-07- x x&& 4)-07- x x&& 0ort! 53!24 x x&& x x&& 0ort" x x&&& 0ort# x x&& 0ort$ x x&& 0ort% x x"&& 0ort& x# x&&& 0ort' x x&& 2eserved x x&& x x"&& x x&& x x&& 53!24 x x"&& x x&& x# x&&& x x&& x x&& 2esetclockcontroller2## x x"&& 0ort( x# x&&& &lashinterface x x&& 2eserved x x&&& #2# x x&& &3-#bank./2032!- x x&&&&&& &3-#bank./2032!- x x&&&&&& &3-#bank./2032!- x x"&&&&&& &3-#bank./2032!- x# x&&&&&&& &3-#bank.!.$.!.$ x x&&&&&&& &3-#bank.!.$.!.$ x x&&&&&&& &3-#bank0##ard x x&&&&&&& &3-#controlregister x! x!&&& x! x"&&&&&&& aic /ption"ytes 4)- 393#&' x x&& x x"&& 3$)/ 2eserved 2eserved x# x&&&& %84) x# x&&& 2eserved "x#!. x x&& x x&& x x"&& x x&&&&&&& 2eserved x x&& $#-) x x&&& 2eserved x x&&&& 53"/4'&3 x x&&&&&&& 2eserved x x&&&& 53"/4'(3 2eserved x x&&&& x x&& %4(%2.%4 2eserved x x&&& x x&& x x&& $-! $-! 2eserved x x&&& x x&&& "+032!- x# x&&& x x"&& 2eserved x x&& 0ort) 4)- 4)- 30) !$# !$# !$# 2eserved "x#!. x# x&&& )# 2eserved 4)- 4)- 4)- x# x&&& x x"&& x x&& 32!-+"aliased bybit banding 2eserved x&&&# x&&&&&&& x&&&! x&&&&&& 2eserved 2eserved x x&&& 2.' 2eserved x x&&& x x&&& 2eserved 2eserved
docid15818 rev 12 67/179 stm32f20xxx electrical characteristics 178 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.8 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 17 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 18 . figure 17. pin loading conditi ons figure 18. pin input voltage -36 #p& -#5pin -36 -#5pin 6 ).
electrical characteristics stm32f20xxx 68/179 docid15818 rev 12 6.1.6 power supply scheme figure 19. power supply scheme 1. each power supply pair must be decoupled with filtering ceramic c apacitors as shown above. these capacitors must be placed as close as possible to , or below, the appropriate pins on the undersi de of the pcb to ensure the good functionality of the device. 2. to connect regoff and irroff pins, refer to section 3.16: voltage regulator . 3. the two 2.2 f ceramic capacitors should be replaced by tw o 100 nf decoupling capacitors when the voltage regulator is off. 4. the 4.7 f ceramic capacitor must be connected to one of the v dd pin. caution: each power supply pair (v dd /v ss , v dda /v ssa ...) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb, to ensure good device operation. it is not recommended to remove filtering capacito rs to reduce pcb size or cost. this might cause incorrect device operation. dli 9 '' 9 %$7 *3,2v 287 ,1 .huqhoorjlf &38 gljlwdo 5$0 %dfnxsflufxlwu\ 26&.57& %dfnxsuhjlvwhuv edfnxs5$0 :dnhxsorjlf ?q) ??) 9 9 66 9 ''$ 9 5() 9 5() 9 66$ $'& /hyhovkliwhu ,2 /rjlf 9 '' q) ?) 9 5() q) ?) 9 '' )odvkphpru\ 9 &$3b 9 &$3b ??) 5(*2)) ,552)) 3rzhuvzlwfk $qdorj 5&v3// 9rowdjh uhjxodwru
docid15818 rev 12 69/179 stm32f20xxx electrical characteristics 178 6.1.7 current consumption measurement figure 20. current consum ption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 11: voltage characteristics , table 12: current characteristics , and table 13: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. ai 6 "!4 6 $$ 6 $$! ) $$ ?6 "!4 ) $$ table 11. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on five-volt tolerant pin (2) 2. v in maximum value must always be respected. refer to table 12 for the values of the maximum allowed injected current. v ss ?0.3 v dd +4 input voltage on any other pin v ss ?0.3 4.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.14: absolute maximum ratings (electrical sensitivity)
electrical characteristics stm32f20xxx 70/179 docid15818 rev 12 6.3 operating conditions 6.3.1 general operating conditions table 12. current characteristics symbol ratings max. unit i vdd total current into v dd power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 120 ma i vss total current out of v ss ground lines (sink) (1) 120 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin 25 i inj(pin) (2) 2. negative injection disturbs the analog performance of the device. see note in section 6.3.20: 12-bit adc characteristics . injected current on five-volt tolerant i/o (3) 3. positive injection is not possible on thes e i/os. a negative injection is induced by v in v dd while a negative injection is induced by v in docid15818 rev 12 71/179 stm32f20xxx electrical characteristics 178 v dd standard operating voltage 1.8 (1) 3.6 v v dda (2) analog operating voltage (adc limited to 1 m samples) must be the same potential as v dd (3) 1.8 (1) 3.6 analog operating voltage (adc limited to 2 m samples) 2.4 3.6 v bat backup operating voltage 1.65 3.6 v in input voltage on rst and ft pins 2v v dd 3.6 v ?0.3 5.5 1.7 v v dd 2 v ?0.3 5.2 input voltage on tta pins ?0.3 v dd +0.3 input voltage on boot0 pin 0 9 v cap1 internal core voltage to be supplied externally in regoff mode 1.1 1.3 v cap2 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (4) lqfp64 - 444 mw wlcsp64+2 - 392 lqfp100 - 434 lqfp144 - 500 lqfp176 - 526 ufbga176 - 513 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low-power dissipation (5) ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low-power dissipation (5) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 1. on devices in wlcsp64+2 package, if irroff is set to v dd , the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range using an external power supply supervisor (see section 3.16 ). 2. when the adc is used, refer to table 66: adc characteristics . 3. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 4. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 5. in low-power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 14. general operating conditions (continued) symbol parameter conditions min max unit
electrical characteristics stm32f20xxx 72/179 docid15818 rev 12 table 15. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency (f flashmax ) number of wait states at maximum cpu frequency (f cpumax = 120 mhz) (1) i/o operation fsmc_clk frequency for synchronous accesses possible flash memory operations v dd =1.8 to 2.1 v (2) conversion time up to 1msps 16 mhz with no flash memory wait state 7 (3) ? degraded speed performance ? no i/o compensation up to 30 mhz 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1msps 18 mhz with no flash memory wait state 6 (3) ? degraded speed performance ? no i/o compensation up to 30 mhz 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2msps 24 mhz with no flash memory wait state 4 (3) ? degraded speed performance ?i/o compensation works up to 48 mhz 16-bit erase and program operations v dd = 2.7 to 3.6 v (4) conversion time up to 2msps 30 mhz with no flash memory wait state 3 (3) ? full-speed operation ?i/o compensation works ?up to 60 mhz when v dd = 3.0 to 3.6 v ?up to 48 mhz when v dd = 2.7 to 3.0 v 32-bit erase and program operations 1. the number of wait states can be reduced by reducing the cpu frequency (see figure 21 ). 2. on devices in wlcsp64+2 package, if irroff is set to v dd , the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range using an external power supply supervisor (see section 3.16 ). 3. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. 4. the voltage range for otg usb fs can drop down to 2.7 v. however it is degraded between 2.7 and 3 v.
docid15818 rev 12 73/179 stm32f20xxx electrical characteristics 178 figure 21. number of wait states versus f cpu and v dd range 1. the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range and irroff is set to v dd . 6.3.2 vcap1/vcap2 external capacitor stabilization for the main regula tor is achieved by connecting an external capacitor to the vcap1/vcap2 pins. c ext is specified in table 16 . figure 22. external capacitor c ext 1. legend: esr is the equivalent series resistance. aib 1xpehuri:dlw vwdwhv )fsx0+] :dlwvwdwhvyv)fsxdqg9''udqjh wr9 wr9 wr9 wr9 table 16. vcap1/vcap2 operating conditions (1) symbol parameter conditions cext capacitance of external capacitor 2.2 f esr esr of external capacitor < 2 069 (65 5 /hdn &
electrical characteristics stm32f20xxx 74/179 docid15818 rev 12 6.3.3 operating conditi ons at power-up / powe r-down (regulator on) subject to general operating conditions for t a . table 17. operating conditions at power-up / power-down (regulator on) 6.3.4 operating conditi ons at power-up / powe r-down (regulator off) subject to general operating conditions for t a . table 18. operating conditions at power-up / power-down (regulator off) 1. when bypassing the voltage regulator, the two 2.2 f v cap capacitors are not required and should be replaced by two 100 nf decoupling capacitors. symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time ra te power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20
docid15818 rev 12 75/179 stm32f20xxx electrical characteristics 178 6.3.5 embedded reset and power control block characteristics the parameters given in table 19 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . table 19. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 v pls[2:0]=001 (rising edge) 2.23 2.30 2.37 v pls[2:0]=001 (falling edge) 2.13 2.19 2.25 v pls[2:0]=010 (rising edge) 2.39 2.45 2.51 v pls[2:0]=010 (falling edge) 2.29 2.35 2.39 v pls[2:0]=011 (rising edge) 2.54 2.60 2.65 v pls[2:0]=011 (falling edge) 2.44 2.51 2.56 v pls[2:0]=100 (rising edge) 2.70 2.76 2.82 v pls[2:0]=100 (falling edge) 2.59 2.66 2.71 v pls[2:0]=101 (rising edge) 2.86 2.93 2.99 v pls[2:0]=101 (falling edge) 2.65 2.84 3.02 v pls[2:0]=110 (rising edge) 2.96 3.03 3.10 v pls[2:0]=110 (falling edge) 2.85 2.93 2.99 v pls[2:0]=111 (rising edge) 3.07 3.14 3.21 v pls[2:0]=111 (falling edge) 2.95 3.03 3.09 v v pvdhyst (1) pvd hysteresis - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 1.68 1.76 v rising edge 1.64 1.72 1.80 v v pdrhyst (1) pdr hysteresis - 40 - mv v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v
electrical characteristics stm32f20xxx 76/179 docid15818 rev 12 6.3.6 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 20: current consumption measurement scheme . all run mode current consumption measurements given in this section are performed using coremark code. v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 v rising edge 2.53 2.59 2.63 v v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 v rising edge 2.85 2.92 2.97 v borhyst (1) bor hysteresis - 100 - mv t rsttempo (1)(2) reset temporization 0.5 1.5 3.0 ms i rush (1) inrush current on voltage regulator power-on (por or wakeup from standby) - 160 200 ma e rush (1) inrush energy on voltage regulator power-on (por or wakeup from standby) v dd = 1.8 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c 1. guaranteed by design, not tested in production. 2. the reset temporization is measured from the power-on (por reset or wakeup from v bat ) to the instant when first instruction is read by the user application code. table 19. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit
docid15818 rev 12 77/179 stm32f20xxx electrical characteristics 178 typical and maximum current consumption the mcu is placed under the following conditions: ? at startup, all i/o pins are configured as analog inputs by firmware. ? all peripherals are disabled except if it is explicitly mentioned. ? the flash memory access time is adjusted to f hclk frequency (0 wait state from 0 to 30 mhz, 1 wait state from 30 to 60 mhz, 2 wait states from 60 to 90 mhz and 3 wait states from 90 to 120 mhz). ? when the peripherals are enabled hclk is the system clock, f pclk1 = f hclk /4, and f pclk2 = f hclk /2, except is explicitly mentioned. ? the maximum values are obtained for v dd = 3.6 v and maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. table 20. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator enabled) or ram (1) symbol parameter conditions f hclk typ max (2) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (3) , all peripherals enabled (4) 120 mhz 49 63 72 ma 90 mhz 38 51 61 60 mhz 26 39 49 30 mhz 14 27 37 25 mhz 11 24 34 16 mhz (5) 82130 8 mhz 5 17 27 4 mhz 3 16 26 2 mhz 2 15 25 external clock (3) , all peripherals disabled 120 mhz 21 34 44 90 mhz 17 30 40 60 mhz 12 25 35 30 mhz 7 20 30 25 mhz 5 18 28 16 mhz (5) 4.0 17.0 27.0 8 mhz 2.5 15.5 25.5 4 mhz 2.0 14.7 24.8 2 mhz 1.6 14.5 24.6 1. code and data processing running from sram1 using boot pins. 2. guaranteed by characterization, tested in production at v dd max and f hclk max with peripherals enabled. 3. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 4. when the adc is on (adon bit set in the adc_cr2 registe r), add an additional power consumption of 1.6 ma per adc for the analog part. 5. in this case hclk = system clock/2.
electrical characteristics stm32f20xxx 78/179 docid15818 rev 12 table 21. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator disabled) symbol parameter conditions f hclk typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled (3) 120 mhz 61 81 93 ma 90 mhz 48 68 80 60 mhz 33 53 65 30 mhz 18 38 50 25 mhz 14 34 46 16 mhz (4) 10 30 42 8 mhz 6 26 38 4 mhz 4 24 36 2 mhz 3 23 35 external clock (2) , all peripherals disabled 120 mhz 33 54 66 90 mhz 27 47 59 60 mhz 19 39 51 30 mhz 11 31 43 25 mhz 8 28 41 16 mhz (4) 62638 8 mhz 4 24 36 4 mhz 3 23 35 2 mhz 2 23 34 1. guaranteed by characterization results, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 3. when the adc is on (adon bit set in the adc_cr2 registe r), add an additional power consumption of 1.6 ma per adc for the analog part. 4. in this case hclk = system clock/2.
docid15818 rev 12 79/179 stm32f20xxx electrical characteristics 178 figure 23. typical current consumption vs temperature, run mode, code with data processing running from ram, and peripherals on figure 24. typical current consumption vs temperature, run mode, code with data processing running from ram, and peripherals off -36 #05frequnecy-(z ?# ?# ?# ?# ?# ?# ?# ) $$25. m! -36 #05&requency-(z ?# ?# ?# ?# ?# ?# ?# ) $$25. m!
electrical characteristics stm32f20xxx 80/179 docid15818 rev 12 figure 25. typical current consumption vs temperature, run mode, code with data processing running from flash, art accelerator off, peripherals on figure 26. typical current consumption vs temperature, run mode, code with data processing running from flash, art accelerator off, peripherals off -36 ?# ?# ) $$25. m! #05frequnecy-(z -36 #05&requency-(z ?# ?# ) $$25. m!
docid15818 rev 12 81/179 stm32f20xxx electrical characteristics 178 table 22. typical and maximum current consumption in sleep mode symbol parameter conditions f hclk typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (2) , all peripherals enabled (3) 120 mhz 38 51 61 ma 90 mhz 30 43 53 60 mhz 20 33 43 30 mhz 11 25 35 25 mhz 8 21 31 16 mhz 6 19 29 8 mhz 3.6 17.0 27.0 4 mhz 2.4 15.4 25.3 2 mhz 1.9 14.9 24.7 external clock (2) , all peripherals disabled 120 mhz 8 21 31 90 mhz 7 20 30 60 mhz 5 18 28 30 mhz 3.5 16.0 26.0 25 mhz 2.5 16.0 25.0 16 mhz 2.1 15.1 25.0 8 mhz 1.7 15.0 25.0 4 mhz 1.5 14.6 24.6 2 mhz 1.4 14.2 24.3 1. guaranteed by characterization results, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 3. add an additional power consumption of 1.6 ma per adc for th e analog part. in applications, th is consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register).
electrical characteristics stm32f20xxx 82/179 docid15818 rev 12 figure 27. typical current consumption vs temperature in sleep mode, peripherals on figure 28. typical current consumption vs temperature in sleep mode, peripherals off -36 ?# ?# ?# ?# ?# ?# ?# )$$ 3,%%0 m! #05&requency-(z -36 ?# ?# ?# ?# ?# ?# ?# #05&requency-(z )$$ 3,%%0 m!
docid15818 rev 12 83/179 stm32f20xxx electrical characteristics 178 figure 29. typical current consumption vs temperature in stop mode 1. all typical and maximum values from table 18 and figur e 26 will be reduced over time by up to 50% as part of st continuous improvement of test procedures. new versions of the datasheet will be released to reflect these changes table 23. typical and maximum current consumptions in stop mode symbol parameter conditions typ max unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop supply current in stop mode with main regulator in run mode flash in stop mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.55 1.2 11.00 20.00 ma flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.50 1.2 11.00 20.00 supply current in stop mode with main regulator in low-power mode flash in stop mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.35 1.1 8.00 15.00 flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.30 1.1 8.00 15.00 -36 4emperature? # )dd?stop?mr?flhstop )dd?stop?mr?flhdeep )dd?stop?lp?flhstop )dd?stop?lp?flhdeep ) $$34/0 m!
electrical characteristics stm32f20xxx 84/179 docid15818 rev 12 table 24. typical and maximum current consumptions in standby mode symbol parameter conditions typ max (1) unit t a = 25 c t a = 85 c t a = 105 c v dd = 1.8 v v dd = 2.4 v v dd = 3.3 v v dd = 3.6 v i dd_stby supply current in standby mode backup sram on, low-speed oscillator and rtc on 3.0 3.4 4.0 15.1 25.8 a backup sram off, low- speed oscillator and rtc on 2.4 2.7 3.3 12.4 20.5 backup sram on, rtc off 2.4 2.6 3.0 12.5 24.8 backup sram off, rtc off 1.7 1.9 2.2 9.8 19.2 1. guaranteed by characterization results, not tested in production. table 25. typical and maximum current consumptions in v bat mode symbol parameter conditions typ max (1) unit t a = 25 c t a = 85 c t a = 105 c v dd = 1.8 v v dd = 2.4 v v dd = 3.3 v v dd = 3.6 v i dd_vbat backup domain supply current backup sram on, low-speed oscillator and rtc on 1.29 1.42 1.68 12 19 a backup sram off, low-speed oscillator and rtc on 0.62 0.73 0.96 8 10 backup sram on, rtc off 0.79 0.81 0.86 9 16 backup sram off, rtc off 0.10 0.10 0.10 5 7 1. guaranteed by characterization results, not tested in production.
docid15818 rev 12 85/179 stm32f20xxx electrical characteristics 178 on-chip peripheral current consumption the current consumption of the on -chip peripherals is given in table 26 . the mcu is placed under the following conditions: ? at startup, all i/o pins are configured as analog inputs by firmware. ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with one peripheral clocked on (with only the clock applied) ? the code is running from flash memory and t he flash memory access time is equal to 3 wait states at 120 mhz ? prefetch and cache on ? when the peripherals are enabled, hclk = 120mhz, f pclk1 = f hclk /4, and f pclk2 =f hclk /2 ? the typical values are obtained for v dd = 3.3 v and t a = 25 c, unless otherwise specified. table 26. peripheral current consumption peripheral (1) typical consumption at 25 c unit ahb1 gpio a 0.45 ma gpio b 0.43 gpio c 0.46 gpio d 0.44 gpio e 0.44 gpio f 0.42 gpio g 0.44 gpio h 0.42 gpio i 0.43 otg_hs + ulpi 3.64 crc 1.17 bkpsram 0.21 dma1 2.76 dma2 2.85 eth_mac + eth_mac_tx eth_mac_rx eth_mac_ptp 2.99 ahb2 otg_fs 3.16 dcmi 0.60 ahb3 fsmc 1.74
electrical characteristics stm32f20xxx 86/179 docid15818 rev 12 apb1 tim2 0.61 ma tim3 0.49 tim4 0.54 tim5 0.62 tim6 0.20 tim7 0.20 tim12 0.36 tim13 0.28 tim14 0.25 usart2 0.25 usart3 0.25 uart4 0.25 uart5 0.26 i2c1 0.25 i2c2 0.25 i2c3 0.25 spi2 0.20/0.10 spi3 0.18/0.09 can1 0.31 can2 0.30 dac channel 1 (2) 1.11 dac channel 1 (3) 1.11 pwr 0.15 wwdg 0.15 table 26. peripheral current consumption (continued) peripheral (1) typical consumption at 25 c unit
docid15818 rev 12 87/179 stm32f20xxx electrical characteristics 178 6.3.7 wakeup time from low-power mode the wakeup times given in table 27 is measured on a wakeup phase with a 16 mhz hsi rc oscillator. the clock source used to wake up the device depends from the current operating mode: ? stop or standby mode: the clo ck source is the rc oscillator ? sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . apb2 sdio 0.69 ma tim1 1.06 tim8 1.03 tim9 0.58 tim10 0.37 tim11 0.39 adc1 (4) 2.13 adc2 (4) 2.04 adc3 (4) 2.12 spi1 1.20 usart1 0.38 usart6 0.37 1. external clock is 25 mh z (hse oscillator with 25 mhz crystal) and pll is on. 2. en1 bit is set in dac_cr register. 3. en2 bit is set in dac_cr register. 4. f adc = f pclk2 /2, adon bit set in adc_cr2 register. table 26. peripheral current consumption (continued) peripheral (1) typical consumption at 25 c unit table 27. low-power mode wakeup timings symbol parameter min (1) typ (1) max (1) unit t wusleep (2) wakeup from sleep mode - 1 - s t wustop (2) wakeup from stop mode (regulator in run mode) - 13 - s wakeup from stop mode (regulator in low-power mode) - 17 40 wakeup from stop mode (regulator in low-power mode and flash memory in deep power down mode) -110- t wustdby (2)(3) wakeup from standby mode 260 375 480 s 1. guaranteed by characterization results, not tested in production. 2. the wakeup times are measured from the wakeup event to the point in which the application c ode reads the first instruction. 3. t wustdby minimum and maximum values are give n at 105 c and ?45 c, respectively.
electrical characteristics stm32f20xxx 88/179 docid15818 rev 12 6.3.8 external clock source characteristics high-speed external user clock generated from an external source the characteristics given in table 28 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 14 . low-speed external user clock generated from an external source the characteristics given in table 29 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 14 . table 28. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) 1-26mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design, not tested in production. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --20 c in(hse) osc_in input capacitance (1) -5-pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a table 29. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) -5-pf ducy (lse) duty cycle 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a
docid15818 rev 12 89/179 stm32f20xxx electrical characteristics 178 figure 30. high-speed external clock source ac timing diagram figure 31. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 30 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). ai /3 # ?) . %xternal 34-& clocksource 6 (3%( t f(3% t 7(3% ) , 4 (3% t t r(3% t 7(3% f (3%?ext 6 (3%, ai / 3#?). %xternal 34-& clocksource 6 ,3%( t f,3% t 7,3% ) , 4 ,3% t t r,3% t 7,3% f ,3%?ext 6 ,3%,
electrical characteristics stm32f20xxx 90/179 docid15818 rev 12 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 32 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on electing the crystal, refer to the app lication note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 32. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 31 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). table 30. hse 4-26 mhz o scillator characteristics (1) (2) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. guaranteed by characterization results, not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 - 26 mhz r f feedback resistor - 200 - k i dd hse current consumption v dd =3.3 v, esr= 30 ? , c l =5 pf@25 mhz -449- a v dd =3.3 v, esr= 30 ? , c l =10 pf@25 mhz -532- g m oscillator transconductance startup 5 - - ma/v t su(hse (3) 3. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms dl 26&b28 7 26&b,1 i +6( & / 5 ) 670) 0+] uhvrqdwru 5hvrqdwruzlwk lqwhjudwhgfdsdflwruv %ldv frqwuroohg jdlq 5 (;7 & /
docid15818 rev 12 91/179 stm32f20xxx electrical characteristics 178 note: for information on electing the crystal, refer to the app lication note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 33. typical applicati on with a 32.768 khz crystal 6.3.9 internal clock source characteristics the parameters given in table 32 and table 33 are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 14 . high-speed internal (hsi) rc oscillator table 31. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit r f feedback resistor - 18.4 - m i dd lse current consumption - - 1 a g m oscillator transconductance 2.8 - - a/v t su(lse) (2) 2. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is m easured for a standard crystal resonator and it can vary significantly with t he crystal manufacturer startup time v dd is stabilized - 2 - s dl 26&b28 7 26&b,1 i /6( & / 5 ) 670) n+ ] uhvrqdwru 5hvrqdwruzlwk lqwhjudwhgfdsdflwruv %ldv frqwuroohg jdlq & / table 32. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 16 - mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) --1% factory- calibrated t a = ?40 to 105 c ?8 - 4.5 % t a = ?10 to 85 c ?4 - 4 % t a = 25 c ?1 - 1 % t su(hsi) (3) hsi oscillator startup time -2.24 s i dd(hsi) hsi oscillator power consumption -6080a
electrical characteristics stm32f20xxx 92/179 docid15818 rev 12 figure 34. acc hsi versus temperature low-speed internal (lsi) rc oscillator 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibrat ion? available from the st website www.st.com. 3. guaranteed by design, not tested in production. table 33. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. guaranteed by characterization results, not tested in production. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a -36 r? r re r? ? e re? r?? r?? r? r? ? ? ?? ?? e? ?? ? ? ?? ?? ? ? ?? e }?uo]]?]}v~9 du????~ u? p u]v
docid15818 rev 12 93/179 stm32f20xxx electrical characteristics 178 figure 35. acc lsi versus temperature 6.3.10 pll characteristics the parameters given in table 34 and table 35 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 14 . -36 .ormalizeddeviati on 4emperat ure?# max avg min table 34. main pll characteristics symbol parameter condi tions min typ max unit f pll_in pll input clock (1) 0.95 (2) 12.10 (2) mhz f pll_out pll multiplier output clock 24 - 120 mhz f pll48_out 48 mhz pll multiplier output clock -- 48mhz f vco_out pll vco output 192 - 432 mhz t lock pll lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300
electrical characteristics stm32f20xxx 94/179 docid15818 rev 12 jitter (3) cycle-to-cycle jitter system clock 120 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - main clock output (mco) for rmii ethernet cycle to cycle at 50 mhz on 1000 samples -32 - main clock output (mco) for mii ethernet cycle to cycle at 25 mhz on 1000 samples -40 - bit time can jitter cycle to cycle at 1 mhz on 1000 samples - 330 - i dd(pll) (4) pll power consumption on vdd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division factor m to obtain the specified pll input clock va lues. the m factor is shared between pll and plli2s. 2. guaranteed by design, not tested in production. 3. the use of 2 plls in parallel could degraded the jitter up to +30%. 4. guaranteed by characterization results, not tested in production. table 34. main pll characteristics (continued) symbol parameter condi tions min typ max unit table 35. plli2s (audio pll) characteristics symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (1) 0.95 (2) 12.10 (2) mhz f plli2s_out plli2s multiplier output clock - - 216 mhz f vco_out plli2s vco output 192 - 432 mhz t lock plli2s lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300
docid15818 rev 12 95/179 stm32f20xxx electrical characteristics 178 jitter (3) master i2s clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12.288 mhz n=432, r=5 on 1000 samples -90 -ps ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps i dd(plli2s) (4) plli2s power consumption on v dd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (4) plli2s power consumption on v dda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division factor m to have the specified pll input clock values. 2. guaranteed by design, not tested in production. 3. value given with main pll running. 4. guaranteed by characterization results, not tested in production. table 35. plli2s (audio pll) characteristics (continued) symbol parameter conditions min typ max unit
electrical characteristics stm32f20xxx 96/179 docid15818 rev 12 6.3.11 pll spread spectrum clo ck generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 42: emi characteristics ). it is available only on the main pll. equation 1 the frequency modulation period (modeper) is given by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz and f mod = 1 khz, the modulation depth (modeper) is given by equation 1: equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and plln = 240 (in mhz): an amplitude quantization error may be generat ed because the linear modulation profile is obtained by taking the quantized values (roun ded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: table 36. sscg parameters constraint symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - 2 15 ? 1- 1. guaranteed by design, not tested in production. modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 250 == incstep round 2 15 1 ? () md plln () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2 240 () 100 5 250 () ? [] 126md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () plln () ? = md quantized % 250 126 100 5 () 2 15 1 ? () 240 () ? 2,0002%(peak) ==
docid15818 rev 12 97/179 stm32f20xxx electrical characteristics 178 figure 36 and figure 37 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 36. pll output clock waveforms in center spread mode figure 37. pll output clock waveforms in down spread mode 6.3.12 memory characteristics flash memory the characteristics are given at t a = ? 40 to 105 c unless otherwise specified. &requency0,,?/54 4ime & tmode xtmode md ai md &requency0,,?/54 4ime & tmode xtmode xmd ai
electrical characteristics stm32f20xxx 98/179 docid15818 rev 12 table 37. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode v dd = 1.8 v -5- ma write / erase 16-bit mode v dd = 2.1 v -8- write / erase 32-bit mode v dd = 3.3 v -12- table 38. flash memory programming symbol parameter conditions min (1) typ max (1) 1. guaranteed by characterization re sults, not tested in production. unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) 2. the maximum programming time is m easured after 100k erase operations. s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.32.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -1632 s program/erase parallelism (psize) = x 16 -1122 program/erase parallelism (psize) = x 32 -816 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.8 - 3.6 v
docid15818 rev 12 99/179 stm32f20xxx electrical characteristics 178 table 40. flash memory endurance and data retention 6.3.13 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. table 39. flash memory programming with v pp symbol parameter conditions min (1) typ max (1) 1. guaranteed by design, not tested in production. unit t prog double word programming t a = 0 to +40 c v dd = 3.3 v v pp = 8.5 v -16100 (2) 2. the maximum programming time is measured after 100k erase operations. s t erase16kb sector (16 kb) erase time - 230 - ms t erase64kb sector (64 kb) erase time - 490 - t erase128kb sector (128 kb) erase time - 875 - t me mass erase time - 6.9 - s v prog programming voltage 2.7 - 3.6 v v pp v pp voltage range 7 - 9 v i pp minimum current sunk on the v pp pin 10 - - ma t vpp (3) 3. v pp should only be connected during programming/erasing. cumulative time during which v pp is applied --1hour symbol parameter conditions value unit min (1) 1. guaranteed by characterization results, not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20
electrical characteristics stm32f20xxx 100/179 docid15818 rev 12 the test results are given in table 41 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 41. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp176, t a = +25 c, f hclk = 120 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp176, t a = +25 c, f hclk = 120 mhz, conforms to iec 61000-4-2 4a
docid15818 rev 12 101/179 stm32f20xxx electrical characteristics 178 electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc ? code, is running. this emission te st is compliant wi th sae iec61967-2 standard which specifies the test board and the pin loading. 6.3.14 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 42. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 25/120 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running with art enabled, peripheral clock disabled 0.1 to 30 mhz 25 dbv 30 to 130 mhz 130 mhz to 1ghz sae emi level 4 - v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running with art enabled, pll spread spectrum enabled, peripheral clock disabled 0.1 to 30 mhz 28 dbv 30 to 130 mhz 26 130 mhz to 1ghz 22 sae emi level 4 - table 43. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to jesd22-a114 2 2000 (2) v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to jesd22-c101 ii 500 1. guaranteed by characterization results, not tested in production. 2. on v bat pin, v esd(hbm) is limited to 1000 v.
electrical characteristics stm32f20xxx 102/179 docid15818 rev 12 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.15 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of spec current injection on adja cent pins or other functional failure (for example reset, oscillator frequency deviation). the test results are given in table 45 . note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 44. electric al sensitivities symbol parameter c onditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 45. i/o current injection susceptibility (1) 1. na stands for ?not applicable?. symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 pin ?0 na ma injected current on nrst pin ?0 na injected current on tta pins: pa4 and pa5 ?0 +5 injected current on all ft pins ?5 na
docid15818 rev 12 103/179 stm32f20xxx electrical characteristics 178 6.3.16 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 50 are derived from tests performed under the conditions summarized in table 14: general operating conditions . all i/os are cmos and ttl compliant. table 46. i/o static characteristics symbol parameter conditions min typ max unit v il ft, tta and nrst i/o input low level voltage 1.7 v v dd 3.6 v - - 0.35v dd ?0.04 (1) v 0.3v dd (2) boot0 i/o input low level voltage 1.75 v v dd 3.6 v, ?40 c t a 105 c -- 0.1v dd +0.1 (1) 1.7 v v dd 3.6 v, 0c t a 105 c -- v ih ft, tta and nrst i/o input high level voltage (5) 1.7 v v dd 3.6 v 0.45v dd +0.3 (1) -- v 0.7v dd (2) boot0 i/o input high level voltage 1.75 v v dd 3.6 v, ?40 c t a 105 c 0.17v dd +0.7 (1) -- 1.7 v v dd 3.6 v, 0c t a 105 c v hys ft, tta and nrst i/o input hysteresis 1.7 v v dd 3.6 v 0.45v dd +0.3 (1) -- v boot0 i/o input hysteresis 1.75 v v dd 3.6 v, ?40 c t a 105 c 10%v ddio (1) (3) -- 1.7 v v dd 3.6 v, 0c t a 105 c 100 (1) -- i lkg i/o input leakage current (4) v ss v in v dd -- 1 a i/o ft input leakage current (5) v in = 5v - - 3
electrical characteristics stm32f20xxx 104/179 docid15818 rev 12 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements for ft i/os is shown in figure 38 . r pu weak pull-up equivalent resistor (6) all pins except for pa10/pb12 (otg_fs_id, otg_hs_id) v in = v ss 30 40 50 k pa10/pb12 (otg_fs_id, otg_hs_id) -71014 r pd weak pull-down equivalent resistor (7) all pins except for pa10/pb12 (otg_fs_id, otg_hs_id) v in = v dd 30 40 50 pa10/pb12 (otg_fs_id, otg_hs_id) -71014 c io (8) i/o pin capacitance - - 5 - pf 1. guaranteed by design, not tested in production. 2. guaranteed by tests in production. 3. with a minimum of 200 mv. 4. leakage could be higher than the maximum value, if negat ive current is injected on adjacent pins, refer to table 45: i/o current injection susceptibility 5. to sustain a voltage higher than vdd +0.3 v, the internal pull-up/pull-down resistors mu st be disabled. leakage could be higher than the maximum value, if negative curr ent is injected on adjacent pins.refer to table 45: i/o current injection susceptibility 6. pull-up resistors are designed with a true resistance in se ries with a switchable pmos. this pmos contribution to the series resistance is minimum (~10% order). 7. pull-down resistors are designed with a true resistance in se ries with a switchable nmos. th is nmos contribution to the series resistance is minimum (~10% order). 8. hysteresis voltage between schmitt trigger switching leve ls. based on characterization, not tested in production. table 46. i/o static characteristics (continued) symbol parameter conditions min typ max unit
docid15818 rev 12 105/179 stm32f20xxx electrical characteristics 178 figure 38. ft i/o input characteristics output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14 and pc15 which can sink or source up to 3ma. when using the pc13 to pc15 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 12 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 12 ). output voltage levels unless otherwise specified, the parameters given in table 47 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . all i/os are cmos and ttl compliant. 069 9''9 9,/9,+9 7hvwhglqsurgxfwlrq&026uhtxluhphqw9,+plq 9'' 7hvwhglqsurgxfwlrq&026uhtxluhphqw9,/pd[ 9'' %dvhgrq'hvljqvlpxodwlrqv9,/pd[ 9'' 77/uhtxluhphqw 9,+plq 9 77/uhtxluhphqw9,/pd[ 9 $uhdqrw ghwhuplqhg %dvhgrq'hvljqvlpxodwlrqv9,+plq 9''
electrical characteristics stm32f20xxx 106/179 docid15818 rev 12 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 39 and table 48 , respectively. unless otherwise specified, the parameters given in table 48 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 14 . table 47. output voltage characteristics (1) 1. pc13, pc14, pc15 and pi8 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these i/os must not be used as a current source (e.g. to drive an led). symbol parameter conditions min max unit v ol (2) 2. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 12 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time cmos ports i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximu m rating specified in table 12 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 - v ol (2) output low level voltage for an i/o pin when 8 pins are sunk at same time ttl ports i io =+ 8ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 - v ol (2)(4) 4. guaranteed by characterization results, not tested in production. output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 - v ol (2)(4) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma 2 v < v dd < 2.7 v -0.4 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 - table 48. i/o ac characteristics (1) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (2) c l = 50 pf, v dd > 2.70 v - - 4 mhz c l = 50 pf, v dd > 1.8 v - - 2 c l = 10 pf, v dd > 2.70 v - - 8 c l = 10 pf, v dd > 1.8 v - - 4 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd = 1.8 v to 3.6 v --100ns
docid15818 rev 12 107/179 stm32f20xxx electrical characteristics 178 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd > 2.70 v - - 25 mhz c l = 50 pf, v dd > 1.8 v - - 12.5 c l = 10 pf, v dd > 2.70 v - - 50 (3) c l = 10 pf, v dd > 1.8 v - - 20 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd >2.7 v - - 10 ns c l = 50 pf, v dd > 1.8 v - - 20 c l = 10 pf, v dd > 2.70 v - - 6 c l = 10 pf, v dd > 1.8 v - - 10 10 f max(io)out maximum frequency (2) c l = 40 pf, v dd > 2.70 v - - 25 mhz c l = 40 pf, v dd > 1.8 v - - 20 c l = 10 pf, v dd > 2.70 v - - 100 (3) c l = 10 pf, v dd > 1.8 v - - 50 (3) t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 40 pf, v dd > 2.70 v - - 6 ns c l = 40 pf, v dd > 1.8 v - - 10 c l = 10 pf, v dd > 2.70 v - 4 c l = 10 pf, v dd > 1.8 v - 6 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd > 2.70 v - - 100 (3) mhz c l = 30 pf, v dd > 1.8 v - - 50 (3) c l = 10 pf, v dd > 2.70 v - - 120 (3) c l = 10 pf, v dd > 1.8 v - - 100 (3) t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 30 pf, v dd > 2.70 v - - 4 ns c l = 30 pf, v dd > 1.8 v - - 6 c l = 10 pf, v dd > 2.70 v - - 2.5 c l = 10 pf, v dd > 1.8 v - - 4 -t extipw pulse width of external signals detected by the exti controller 10 - - ns 1. the i/o speed is configured using the ospeedry[1:0] bits . refer to the stm32f20/21xxx reference manual for a description of the gpiox_speedr gpio port output speed register. 2. the maximum frequency is defined in figure 39 . 3. for maximum frequencies above 50 mhz and v dd above 2.4 v, the compensation cell should be used. table 48. i/o ac characteristics (1) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit
electrical characteristics stm32f20xxx 108/179 docid15818 rev 12 figure 39. i/o ac charac teristics definition 6.3.17 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 49 ). unless otherwise specified, the parameters given in table 49 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 14 . figure 40. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in dlg w u,2rxw 287387 (;7(51$/ 21&/ 0d[lpxpiuhtxhqf\lvdfklhyhgliw u w i ?7dqgliwkhgxw\f\fohlv zkhqordghge\& / vshflilhglqwkhwdeoh3 ,2$&fkdudfwhulvwlfv 7 w i,2rxw table 49. nrst pin characteristics symbol parameter conditions min typ max unit r pu weak pull-up equivalent resistor (1) v in = v ss 30 40 50 k v f(nrst) (2) nrst input filtered pulse - - 100 ns v nf(nrst) (2) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s 1. the pull-up is designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . 2. guaranteed by design, not tested in production. dlf 670) 5 38 1567 9 '' )lowhu ,qwhuqdo5hvhw ?) ([whuqdo uhvhwflufxlw
docid15818 rev 12 109/179 stm32f20xxx electrical characteristics 178 table 49 . otherwise the reset is not taken into account by the device. 6.3.18 tim time r characteristics the parameters given in table 50 and table 51 are guaranteed by design. refer to section 6.3.16: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). table 50. characteristics of timx connected to the apb1 domain (1) 1. timx is used as a general term to refer to the tim2, tim3, tim4, tim5, tim6, tim7, and tim12 timers. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb1 prescaler distinct from 1, f timxclk = 60 mhz 1- t timxclk 16.7 - ns ahb/apb1 prescaler = 1, f timxclk = 30 mhz 1- t timxclk 33.3 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 60 mhz apb1= 30 mhz 0 f timxclk /2 mhz 030mhz res tim timer resolution - 16/32 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk 0.0167 1092 s 32-bit counter clock period when internal clock is selected 1- t timxclk 0.0167 71582788 s t max_count maximum possible count - 65536 65536 t timxclk - 71.6 s
electrical characteristics stm32f20xxx 110/179 docid15818 rev 12 6.3.19 communications interfaces i 2 c interface characteristics stm32f205xx and stm32f207xx i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following re strictions: the i/o pins sda and scl are mapped to are not ?true? open-drain. when co nfigured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 52 . refer also to section 6.3.16: i/o port characteristics for more details on the input/output al ternate function characteristics (sda and scl) . table 51. characteristics of timx connected to the apb2 domain (1) 1. timx is used as a general term to refer to the tim1, tim8, tim9, tim10, and tim11 timers. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb2 prescaler distinct from 1, f timxclk = 120 mhz 1- t timxclk 8.3 - ns ahb/apb2 prescaler = 1, f timxclk = 60 mhz 1- t timxclk 16.7 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 120 mhz apb2 = 60 mhz 0 f timxclk /2 mhz 060mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk 0.0083 546 s t max_count maximum possible count - 65536 65536 t timxclk - 35.79 s
docid15818 rev 12 111/179 stm32f20xxx electrical characteristics 178 table 52. i 2 c characteristics symbol parameter standard mode i 2 c (1)(2) 1. guaranteed by design, not tested in production. fast mode i 2 c (1)(2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies, and a multiple of 10 mhz to reach the 400 khz maximum i 2 c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time - 3450 (3) -900 (3) 3. the maximum data hold time has only to be met if t he interface does not stretch the low period of the scl signal. t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf t sp pulse width of the spikes that are suppressed by the analog filter 050 (4) 4. the minimum width of the spikes fi ltered by the analog filter is above t sp(max) . 050ns
electrical characteristics stm32f20xxx 112/179 docid15818 rev 12 figure 41. i 2 c bus ac waveforms and measurement circuit 1. r s = series protection resistor. 2. r p = external pull-up resistor. 3. v dd_i2c is the i 2 c bus power supply. table 53. scl frequency (f pclk1 = 30 mhz.,v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012c 20 0x02ee dlf 5 3 ,e&exv s ''b,& 670)[[ 6'$ 6&/ w i6'$ w u6'$ w k67$ w z6&// w z6&/+ w vx6'$ w u6&/ w i6&/ w k6'$ 67$575(3($7(' w vx67$ w vx672 6723 w z67267$ s ''b,& 5 3 5 6 5 6 67$57 67$57 6'$ 6&/
docid15818 rev 12 113/179 stm32f20xxx electrical characteristics 178 i 2 s - spi interface characteristics unless otherwise specified, the parameters given in table 54 for spi or in table 55 for i 2 s are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 14 . refer to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (n ss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 54. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency spi1 master/slave mode - 30 mhz spi2/spi3 master/slave mode - 15 t r(scl) t f(scl) spi clock rise and fall time capacitive load: c = 30 pf, f pclk = 30 mhz - 8ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (1) 1. guaranteed by characterization results, not tested in production. nss setup time slave mode 4t pclk - ns t h(nss) (1) nss hold time slave mode 2t pclk - t w(sclh) (1) t w(scll) (1) sck high and low time master mode, f pclk = 30 mhz, presc = 2 t pclk - 3t pclk +3 t su(mi) (1) t su(si) (1) data input setup time master mode 5 - slave mode 5 - t h(mi) (1) t h(si) (1) data input hold time master mode 5 - slave mode 4 - t a(so) (1)(2) 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 30 mhz 0 3t pclk t dis(so) (1)(3) 3. min time is for the minimum time to invalidate the out put and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (1) data output valid time slave mode (after enable edge) - 25 t v(mo) (1) data output valid time master mode (after enable edge) - 5 t h(so) (1) data output hold time slave mode (after enable edge) 15 - t h(mo) (1) master mode (after enable edge) 2 -
electrical characteristics stm32f20xxx 114/179 docid15818 rev 12 figure 42. spi timing diagram - slave mode and cpha = 0 figure 43. spi timing diagram - slave mode and cpha = 1 ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
docid15818 rev 12 115/179 stm32f20xxx electrical characteristics 178 figure 44. spi timing diagram - master mode ai6 3#+/utput #0(! -/3) /54054 -)3/ ).0 54 #0(! -3 "). - 3"/54 ") 4). ,3"/54 ,3"). #0/, #0/, " ) 4/54 .33input t c3#+ t w3#+( t w3#+, t r3#+ t f3#+ t h-) (igh 3#+/utput #0(! #0(! #0/, #0/, t su-) t v-/ t h-/
electrical characteristics stm32f20xxx 116/179 docid15818 rev 12 table 55. i 2 s characteristics symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master, 16-bit data, audio frequency = 48 khz, main clock disabled 1.23 1.24 mhz slave 0 64f s (1) t r(ck) t f(ck) i 2 s clock rise and fall time capacitive load c l = 50 pf - (2) ns t v(ws) (3) ws valid time master 0.3 - t h(ws) (3) ws hold time master 0 - t su(ws) (3) ws setup time slave 3 - t h(ws) (3) ws hold time slave 0 - t w(ckh) (3) t w(ckl) (3) ck high and low time master f pclk = 30 mhz 396 - t su(sd_mr) (3) t su(sd_sr) (3) data input setup time master receiver slave receiver 45 0 - t h(sd_mr) (3)(4) t h(sd_sr) (3)(4) data input hold time master receiver: f pclk = 30 mhz, slave receiver: f pclk = 30 mhz 13 0 - t v(sd_st) (3)(4) data output valid time slave transmitter (after enable edge) - 30 t h(sd_st) (3) data output hold time slave transmitter (after enable edge) 10 - t v(sd_mt) (3)(4) data output valid time master transmitter (after enable edge) - 6 t h(sd_mt) (3) data output hold time master transmitter (after enable edge) 0- 1. f s is the sampling frequency. refer to the i2s section of t he stm32f20xxx/21xxx reference manual for more details. f ck values reflect only the digita l peripheral behavior which leads to a minimu m of (i2sdiv/(2*i2sdiv+odd), a maximum of (i2sdiv+odd)/(2*i2sdiv+odd) and f s maximum values for each mode/condition. 2. refer to table 48: i/o ac characteristics . 3. guaranteed by design, not tested in production. 4. depends on f pclk . for example, if f pclk =8 mhz, then t pclk = 1/f plclk =125 ns.
docid15818 rev 12 117/179 stm32f20xxx electrical characteristics 178 figure 45. i 2 s slave timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 46. i 2 s master timing diagram (philips protocol) (1) 1. guaranteed by characterization re sults, not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14881b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14884b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2)
electrical characteristics stm32f20xxx 118/179 docid15818 rev 12 usb otg fs characteristics the usb otg interface is u sb-if certified (full-spee d). this interface is present in both the usb otg hs and usb otg fs controllers. table 56. usb otg fs startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb otg fs transceiver startup time 1 s table 57. usb otg fs dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg fs operating voltage 3.0 (2) 2. the stm32f205xx and stm32f207xx usb otg fs functionality is ensured down to 2.7 v but not the full usb otg fs electrical c haracteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. -3.6v v di (3) 3. guaranteed by design, not tested in production. differential input sensitivity i(usb_fs_dp/dm, usb_hs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold 1.3 - 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb otg fs drivers --0.3 v v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12, pb14, pb15 (usb_fs_dp/dm, usb_hs_dp/dm) v in = v dd 17 21 24 k pa9, pb13 (otg_fs_vbus, otg_hs_vbus) 0.65 1.1 2.0 r pu pa12, pb15 (usb_fs_dp, usb_hs_dp) v in = v ss 1.5 1.8 2.1 pa9, pb13 (otg_fs_vbus, otg_hs_vbus) v in = v ss 0.25 0.37 0.55
docid15818 rev 12 119/179 stm32f20xxx electrical characteristics 178 figure 47. usb otg fs timings: definiti on of data signal rise and fall time usb hs characteristics table 59 shows the usb hs operating voltage. table 58. usb otg fs el ectrical characteristics (1) 1. guaranteed by design, not tested in production. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal cro ssover voltage 1.3 2.0 v table 59. usb hs dc elect rical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd usb otg hs operating voltage 2.7 3.6 v table 60. clock timing parameters parameter (1) 1. guaranteed by design, not tested in production. symbol min nominal max unit frequency (first transition) 8-bit 10% f start_8bit 54 60 66 mhz frequency (steady state) 500 ppm f steady 59.97 60 60.03 mhz duty cycle (first transition) 8-bit 10% d start_8bit 40 50 60 % duty cycle (steady state) 500 ppm d steady 49.975 50 50.025 % time to reach the steady state frequency and duty cycle after the first transition t steady --1.4ms clock startup time after the de-assertion of suspendm peripheral t start_dev --5.6 ms host t start_host --- phy preparation time after the first transition of the input clock t prep ---s ai14137 t f differen tial data l ines v ss v cr s t r crossover points
electrical characteristics stm32f20xxx 120/179 docid15818 rev 12 figure 48. ulpi timing diagram ethernet characteristics table 62 shows the ethernet operating voltage. table 63 gives the list of ethernet mac signals for the smi (station management interface) and figure 49 shows the corresponding timing diagram. table 61. ulpi timing symbol parameter value (1) 1. v dd = 2.7 v to 3.6 v and t a = ?40 to 85 c. unit min. max. t sc control in (ulpi_dir) setup time - 2.0 ns control in (ulpi_nxt) setup time - 1.5 t hc control in (ulpi_dir, ulpi_nxt) hold time 0 - t sd data in setup time - 2.0 t hd data in hold time 0 - t dc control out (ulpi_stp) setup time and hold time - 9.2 t dd data out available from clock rising edge - 10.7 table 62. ethernet dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd ethernet operatin g voltage 2.7 3.6 v #lock #ontrol)n 5,0)?$)2 5,0)?.84 data)n bit #ontrolout 5,0)?340 dataout bit t $$ t $# t ($ t 3$ t (# t 3# aic t $#
docid15818 rev 12 121/179 stm32f20xxx electrical characteristics 178 figure 49. ethernet smi timing diagram table 64 gives the list of ethernet mac signals for the rmii and figure 50 shows the corresponding timing diagram. figure 50. ethernet rmii timing diagram table 63. dynamics characteristics: ethernet mac signals for smi symbol rating min typ max unit t mdc mdc cycle time (2.38 mhz) 411 420 425 ns t d(mdio) mdio write data valid time 6 10 13 ns t su(mdio) read data setup time 12 - - ns t h(mdio) read data hold time 0 - - ns table 64. dynamics characteristics: ethernet mac signals for rmii symbol rating min typ max unit t su(rxd) receive data setup time 1 - - ns t ih(rxd) receive data hold time 1.5 - - t su(crs) carrier sense set-up time 0 - - t ih(crs) carrier sense hold time 2 - - t d(txen) transmit enable valid delay time 9 11 13 t d(txd) transmit data valid delay time 9 11.5 14 %4(?-$# %4(?-$)// %4(?-$)/) t -$# t d-$)/ t su-$)/ t h-$)/ aid rmii_ref_clk rmii_tx_en rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv t d(txen) t d(txd) t su(rxd) t su(crs) t ih(rxd) t ih(crs) ai15667
electrical characteristics stm32f20xxx 122/179 docid15818 rev 12 table 65 gives the list of ethernet mac signals for mii and figure 50 shows the corresponding timing diagram. figure 51. ethernet mii timing diagram can (controller area network) interface refer to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (cantx and canrx). table 65. dynamics characteristics: ethernet mac signals for mii symbol rating min typ max unit t su(rxd) receive data setup time 7.5 - - ns t ih(rxd) receive data hold time 1 - - ns t su(dv) data valid setup time 4 - - ns t ih(dv) data valid hold time 0 - - ns t su(er) error setup time 3.5 - - ns t ih(er) error hold time 0 - - ns t d(txen) transmit enable valid delay time - 11 14 ns t d(txd) transmit data valid delay time - 11 14 ns mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er t d(txen) t d(txd) t su(rxd) t su(er) t su(dv) t ih(rxd) t ih(er) t ih(dv) ai1566 8 mii_tx_clk mii_tx_en mii_txd[3:0]
docid15818 rev 12 123/179 stm32f20xxx electrical characteristics 178 6.3.20 12-bit adc characteristics unless otherwise specified, the parameters given in table 66 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions su mmarized in table 14 . table 66. adc characteristics symbol parameter conditions min typ max unit v dda power supply 1.8 (1) -3.6v v ref+ positive reference voltage 1.8 (1)(2) -v dda v f adc adc clock frequency v dda = 1.8 (1) to 2.4 v 0.6 - 15 mhz v dda = 2.4 to 3.6 v 0.6 - 30 mhz f trig (3) external trigger frequency f adc = 30 mhz with 12-bit resolution - - 1764 khz - - 17 1/f adc v ain conversion voltage range (4) 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (3) external input impedance see equation 1 for details --50k r adc (3)(5) sampling switch resistance 1.5 - 6 k c adc (3) internal sample and hold capacitor -4-pf t lat (3) injection trigger conversion latency f adc = 30 mhz - - 0.100 s --3 (6) 1/f adc t latr (3) regular trigger conversion latency f adc = 30 mhz - - 0.067 s --2 (6) 1/f adc t s (3) sampling time f adc = 30 mhz 0.100 - 16 s 3-4801/f adc t stab (3) power-up time - 2 3 s t conv (3) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.5 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 s f adc = 30 mhz 8-bit resolution 0.37 - 16.27 s f adc = 30 mhz 6-bit resolution 0.3 - 16.20 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc
electrical characteristics stm32f20xxx 124/179 docid15818 rev 12 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. a note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this signifi cantly reduces the accuracy of the conversion f s (3) sampling rate (f adc = 30 mhz) 12-bit resolution single adc - - 2 msps 12-bit resolution interleave dual adc mode --3.75msps 12-bit resolution interleave triple adc mode - - 6 msps i vref+ (3) adc v ref dc current consumption in conversion mode -300500a i vdda (3) adc vdda dc current consumption in conversion mode -1.61.8ma 1. on devices in wlcsp64+2 package, if irroff is set to v dd , the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range us ing an external power supply supervisor (see section 3.16 ). 2. it is recommended to maintain the voltage difference between v ref+ and v dda below 1.8 v. 3. guaranteed by characterization results, not tested in production. 4. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 5. r adc maximum value is given for v dd =1.8 v, and minimum value for v dd =3.3 v. 6. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 66 . table 66. adc characteristics (continued) symbol parameter conditions min typ max unit table 67. adc accuracy (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. guaranteed by characterization results, not tested in production. unit et total unadjusted error f pclk2 = 60 mhz, f adc = 30 mhz, r ain < 10 k , v dda = 1.8 (3) to 3.6 v 3. on devices in wlcsp64+2 package, if irroff is set to v dd , the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range using an external power supply supervisor (see section 3.16 ). 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 r ain k0,5 ? () f adc c adc 2 n 2 + () ln -------------------------------------------------------------- r adc ? =
docid15818 rev 12 125/179 stm32f20xxx electrical characteristics 178 being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.16 does not affect the adc accuracy. figure 52. adc accuracy characteristics 1. example of an actual transfer curve. 2. ideal transfer curve. 3. end point correlation line. 4. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum deviation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual transition and the end point correlation line. figure 53. typical connecti on diagram using the adc 1. refer to table 66 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value downgrades conversion accuracy. to remedy this, f adc should be reduced. aic % / % ' , 3" )$%!, % 4 % $ % , 6 $$! 6 33! 6 2%& ordependingonpackage = 6 $$! ;,3" )$%!, dl 670) 9 '' $,1[ , / ??$ 9 9 7 5 $,1 & sdudvlwlf 9 $,1 9 9 7 5 $'& & $'& elw frqyhuwhu 6dpsohdqgkrog$'& frqyhuwhu
electrical characteristics stm32f20xxx 126/179 docid15818 rev 12 general pcb design guidelines power supply decoupling should be performed as shown in figure 54 or figure 55 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 54. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176 package. v ref+ is also available on all packages except for lqfp64. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . figure 55. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176 package. v ref+ is also available on all packages except for lqfp64. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . v ref+ s tm 3 2f v dda v ss a /v ref- 1 f // 10 nf 1 f // 10 nf a i175 3 5 ( s ee note 1) ( s ee note 1) v ref+ /v dda s tm 3 2f 1 f // 10 nf v ref? /v ss a a i175 3 6 ( s ee note 1) ( s ee note 1)
docid15818 rev 12 127/179 stm32f20xxx electrical characteristics 178 6.3.21 dac electri cal characteristics table 68. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 1.8 (1) -3.6 v v ref+ reference supply voltage 1.8 (1) -3.6vv ref+ v dda v ssa ground 0 - 0 v r load (2) resistive load with buffer on 5 - - k r o (2) impedance output with buffer off -- 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (2) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.8 v dac_out max (2) higher dac_out voltage with buffer on --v dda ? 0.2 v dac_out min (2) lower dac_out voltage with buffer off -0.5 - mv it gives the maximum output excursion of the dac. dac_out max (2) higher dac_out voltage with buffer off --v ref+ ? 1lsb v i vref+ (4) dac dc v ref current consumption in quiescent mode (standby mode) - 170 240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs -50 75 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda (4) dac dc v dda current consumption in quiescent mode (3) - 280 380 a with no load, middle code (0x800) on the inputs - 475 625 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (4) differential non linearity difference between two consecutive code-1lsb) -- 0.5 lsb given for the dac in 10-bit configuration. -- 2 lsb given for the dac in 12-bit configuration.
electrical characteristics stm32f20xxx 128/179 docid15818 rev 12 inl (4) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) -- 1 lsb given for the dac in 10-bit configuration. -- 4 lsb given for the dac in 12-bit configuration. offset (4) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) -- 10 mv -- 3 lsb given for the dac in 10-bit at v ref+ = 3.6 v -- 12lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (4) gain error - - 0.5 % given for the dac in 12-bit configuration t settling (4) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 4lsb -3 6 s c load 50 pf, r load 5 k thd (4) total harmonic distortion buffer on -- - db c load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1 ms/s c load 50 pf, r load 5 k t wakeup (4) wakeup time from off state (setting the enx bit in the dac control register) - 6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement) - ?67 ?40 db no r load , c load = 50 pf 1. on devices in wlcsp64+2 package, if irroff is set to v dd , the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range using an external power supply supervisor (see section 3.16 ). 2. guaranteed by design, not tested in production. 3. the quiescent mode corresponds to a state where the dac ma intains a stable output level to ensure that no dynamic consumption occurs. 4. guaranteed by characterization results, not tested in production. table 68. dac characteristics (continued) symbol parameter min typ max unit comments
docid15818 rev 12 129/179 stm32f20xxx electrical characteristics 178 figure 56. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 6.3.22 temperature sensor characteristics 6.3.23 v bat monitoring characteristics r l c l buffered/non-buffered dac dac_outx buffer(1) 12-bit digital to analog converter ai17157v2 table 69. temperature sensor characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by characterization results, not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 mv/c v 25 (1) voltage at 25 c - 0.76 v t start (2) 2. guaranteed by design, not tested in production. startup time - 6 10 s t s_temp (2) adc sampling time when reading the temperature 1c accuracy 10 - - s table 70. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q ?1 - +1 % t s_vbat (2)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat 1mv accuracy 5- -s
electrical characteristics stm32f20xxx 130/179 docid15818 rev 12 6.3.24 embedded reference voltage the parameters given in table 71 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . 6.3.25 fsmc characteristics asynchronous waveforms and timings figure 57 through figure 60 represent asynchronous waveforms and table 72 through table 75 provide the corresponding ti mings. the results shown in these tables are obtained with the following fsmc configuration: ? addresssetuptime = 1 ? addressholdtime = 1 ? datasetuptime = 1 ? busturnaroundduration = 0x0 in all timing tables, the t hclk is the hclk clock period. table 71. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 10 - - s v rerint_s (2) 2. guaranteed by design, not tested in production. internal reference voltage spread over the temperature range v dd = 3 v - 3 5 mv t coeff (2) temperature coefficient - 30 50 ppm/c t start (2) startup time - 6 10 s
docid15818 rev 12 131/179 stm32f20xxx electrical characteristics 178 figure 57. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 72. asynchronous non-multipl exed sram/psram/nor read timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 2t hclk ? 0.5 2t hclk +0.5 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 0.5 2.5 ns t w(noe) fsmc_noe low time 2t hclk - 1 2t hclk + 0.5 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 4 ns t h(a_noe) address hold time after fsmc_noe high 0 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0.5 ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0 - ns t su(data_ne) data to fsmc_nex high setup time t hclk + 0.5 - ns t su(data_noe) data to fsmc_noex high setup time t hclk + 2.5 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 2.5 ns t w(nadv ) fsmc_nadv low time - t hclk ? 0.5 ns $ata &3-#?.% &3-#?.",;= &3-#?$;= t v",?.% t h$ata?.% &3-#?./% !ddress &3-#?!;= t v!?.% &3-#?.7% t su$ata?.% t w.% aic w./% t t v./%?.% t h.%?./% t h$ata?./% t h!?./% t h",?./% t su$ata?./% &3-#?.!$6 t v.!$6?.% t w.!$6
electrical characteristics stm32f20xxx 132/179 docid15818 rev 12 figure 58. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production. table 73. asynchronous non-multipl exed sram/psram/nor write timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk 3t hclk + 4 ns t v(nwe_ne ) fsmc_nex low to fsmc_nwe low t hclk ? 0.5 t hclk + 0.5 ns t w(nwe) fsmc_nwe low time t hclk ? 0.5 t hclk + 3 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk -ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t h(a_nwe) address hold time after fsmc_nwe high t hclk - 3 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1 - ns t v(data_ne) data to fsmc_nex low to data valid - t hclk + 5 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk +0.5 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 2 ns t w(nadv) fsmc_nadv low time - t hclk + 1.5 ns 1%/ 'dwd )60&b1([ )60&b1%/>@ )60&b'>@ w y%/b1( w k'dwdb1:( )60&b12( $gguhvv )60&b$>@ w y$b1( w z1:( )60&b1:( w y1:(b1( w k1(b1:( w k$b1:( w k%/b1:( w y'dwdb1( w z1( dl )60&b1$'9 w y1$'9b1( w z1$'9
docid15818 rev 12 133/179 stm32f20xxx electrical characteristics 178 figure 59. asynchronous multiplexed psram/nor read waveforms 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production. table 74. asynchronous multiplexed psram/nor read timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk -1 3t hclk +1 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 2t hclk 2t hclk +0.5 ns t w(noe) fsmc_noe low time t hclk -1 t hclk +1 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 2 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 1 2.5 ns t w(nadv) fsmc_nadv low time t hclk ? 1.5 t hclk ns t h(ad_nadv) fsmc_ad(adress) valid hold time after fsmc_nadv high) t hclk -ns t h(a_noe) address hold time after fsmc_noe high t hclk -ns t h(bl_noe) fsmc_bl time after fsmc_noe high 0 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1 ns t su(data_ne) data to fsmc_nex high setup time t hclk + 2 - ns .", $ata &3-#?.",;= &3-#? !$;= t v",?.% t h$ata?.% !ddress &3-#?!;= t v!?.% &3-#?.7% t v!?.% aib !ddress &3-#?.!$6 t v.!$6?.% t w.!$6 t su$ata?.% t h!$?.!$6 &3-#?.% &3-#?./% t w.% t w./% t v./%?.% t h.%?./% t h!?./% t h",?./% t su$ata?./% t h$ata?./%
electrical characteristics stm32f20xxx 134/179 docid15818 rev 12 t su(data_noe) data to fsmc_noe high setup time t hclk + 3 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production. table 74. asynchronous multip lexed psram/nor read timings (1)(2) (continued) symbol parameter min max unit
docid15818 rev 12 135/179 stm32f20xxx electrical characteristics 178 figure 60. asynchronous multip lexed psram/nor write waveforms table 75. asynchrono us multiplexed psram /nor write timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 4t hclk -1 4t hclk +1 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk - 1 t hclk ns t w(nwe) fsmc_nwe low tim e 2t hclk 2t hclk +1 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk - 1 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 1 2 ns t w(nadv) fsmc_nadv low time t hclk ? 2 t hclk + 2 ns t h(ad_nadv) fsmc_ad(adress) valid hold time after fsmc_nadv high) t hclk -ns t h(a_nwe) address hold time after fsmc_nwe high t hclk ? 0.5 - ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk - 1 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0.5 ns t v(data_nadv) fsmc_nadv high to data valid - t hclk +2 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk ? 0.5 - ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:16] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(a_ne) t w(ne) ai14 8 91b address fsmc_nadv t v(nadv_ne) t w(nadv) t v(data_nadv) t h(ad_nadv)
electrical characteristics stm32f20xxx 136/179 docid15818 rev 12 synchronous waveforms and timings figure 61 through figure 64 represent synchronous waveforms and table 77 through table 79 provide the corresponding ti mings. the results shown in these tables are obtained with the following fsmc configuration: ? burstaccessmode = fsmc_burstaccessmode_enable; ? memorytype = fsmc_memorytype_cram; ? writeburst = fsmc_writeburst_enable; ? clkdivision = 1; (0 is not supported, see the stm32f20xxx/21xxx reference manual) ? datalatency = 1 for nor flash; datalatency = 0 for psram in all timing tables, the t hclk is the hclk clock period. figure 61. synchronous multiplexed nor/psram read timings )60&b&/. )60&b1([ )60&b1$'9 )60&b$>@ )60&b12( )60&b$'>@ $'>@ ' ' )60&b1:$,7 :$,7&)* e:$,732/e )60&b1:$,7 :$,7&)* e:$,732/e w z&/. w z&/. 'dwdodwhqf\ %867851 w g&/./1([/ w g&/./1([+ w g&/./1$'9/ w g&/./$9 w g&/./1$'9+ w g&/./$,9 w g&/.+12(/ w g&/./12(+ w g&/./$'9 w g&/./$',9 w vx$'9&/.+ w k&/.+$'9 w vx$'9&/.+ w k&/.+$'9 w vx1:$,79&/.+ w k&/.+1:$,79 w vx1:$,79&/.+ w k&/.+1:$,79 w vx1:$,79&/.+ w k&/.+1:$,79 dlk
docid15818 rev 12 137/179 stm32f20xxx electrical characteristics 178 table 76. synchronous multiplexed nor/psram read timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 1.5 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 2.5 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 0 - ns t d(clkh-noel) fsmc_clk high to fsmc_noe low - 1 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1 - ns t d(clkl-adv) fsmc_clk low to fsmc _ad[15:0] valid - 3 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 - ns t su(adv-clkh) fsmc_a/d[15:0] valid data before fsmc_clk high 5 -ns t h(clkh-adv) fsmc_a/d[15:0] valid data after fsmc_clk high 0 - ns
electrical characteristics stm32f20xxx 138/179 docid15818 rev 12 figure 62. synchronous multiplexed psram write timings table 77. synchronous multiplexed psram write timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization re sults, not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk - 1 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 2 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 2 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 3 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 7 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 0 - ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 - ns t d(clkl-data ) fsmc_a/d[15:0] valid data after fsmc_clk low - 2 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 0.5 - ns &3-#?#,+ &3-#?.%x &3-#?.!$6 &3-#?!;= &3-#?.7% &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+, !)6 t d#,+, .7%( t d#,+, .7%, t d#,+, .",( t d#,+, !$6 t d#,+, !$)6 t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 aig t d#,+, $ata &3-#?.",
docid15818 rev 12 139/179 stm32f20xxx electrical characteristics 178 figure 63. synchronous non-multiplexed nor/psram read timings table 78. synchronous non-multipl exed nor/psram read timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 2.5 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 4 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 3 - ns t d(clkh-noel) fsmc_clk high to fsmc_noe low - 1 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1.5 - ns t su(dv-clkh) fsmc_d[15:0] valid data before fsmc_clk high 8 - ns t h(clkh-dv) fsmc_d[15:0] valid data after fsmc_clk high 0 - ns &3-#?#,+ &3-#?.%x &3-#?!;= &3-#?./% &3-#?$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, !6 t d#,+, !)6 t d#,+( ./%, t d#,+, ./%( t su$6 #,+( t h#,+( $6 t su$6 #,+( t h#,+( $6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 aig &3-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( $
electrical characteristics stm32f20xxx 140/179 docid15818 rev 12 figure 64. synchronous non-multi plexed psram write timings table 79. synchronous non-multiplexed psram write timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization re sults, not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk - 1 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 1 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl- nadvl) fsmc_clk low to fsmc_nadv low - 5 ns t d(clkl- nadvh) fsmc_clk low to fsmc_nadv high 6 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 8 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1 - ns t d(clkl-data) fsmc_d[15:0] valid data after fsmc_clk low - 2 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 2 - ns &3-#?#,+ &3-#?.%x &3-#?!;= &3-#?.7% &3-#?$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, !6 t d#,+, !)6 t d#,+, .7%( t d#,+, .7%, t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 aig &3-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( t d#,+, $ata &3-#?.", t d#,+, .",(
docid15818 rev 12 141/179 stm32f20xxx electrical characteristics 178 pc card/compactflash controller waveforms and timings figure 65 through figure 70 represent synchronous waveforms together with table 80 and table 81 provides the corresponding timings. the results shown in this table are obtained with the following fsmc configuration: ? com.fsmc_setuptime = 0x04; ? com.fsmc_waitsetuptime = 0x07; ? com.fsmc_holdsetuptime = 0x04; ? com.fsmc_hizsetuptime = 0x00; ? att.fsmc_setuptime = 0x04; ? att.fsmc_waitsetuptime = 0x07; ? att.fsmc_holdsetuptime = 0x04; ? att.fsmc_hizsetuptime = 0x00; ? io.fsmc_setuptime = 0x04; ? io.fsmc_waitsetuptime = 0x07; ? io.fsmc_holdsetuptime = 0x04; ? io.fsmc_hizsetu ptime = 0x00; ? tclrsetuptime = 0; ? tarsetuptime = 0; in all timing tables, the t hclk is the hclk clock period. figure 65. pc card/compactflash controll er waveforms for common memory read access 1. fsmc_nce4_2 remains high (inac tive during 8-bit access. )60&b1:( w z12( )60&b1 2( )60&b'>@ )60&b$>@ )60&b1&(b )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25' w g1&(b12( w vx'12( w k12(' w y1&([$ w g15(*1&([ w g1,25'1&([ w k1&([$, w k1&([15(* w k1&([1,25' w k1&([ 1,2:5 dle
electrical characteristics stm32f20xxx 142/179 docid15818 rev 12 figure 66. pc card/compactflash contro ller waveforms for co mmon memory write access w g1&(b1:( w z1:( w k1:(' w y1&(b$ w g15(*1&(b w g1,25'1&(b w k1&(b$, 0(0[+,= w y1:(' w k1&(b15(* w k1&(b1,25' w k1&(b1,2:5 dle )60&b1:( )60&b1 2( )60&b'>@ )60&b$>@ )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25' w g1:(1&(b w g'1:( )60&b1&(b +ljk
docid15818 rev 12 143/179 stm32f20xxx electrical characteristics 178 figure 67. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). w g1&(b12( w z12( w vx'12( w k12(' w y1&(b$ w k1&(b$, w g15(*1&(b w k1&(b15(* dle )60&b1:( )60&b12( )60&b'>@ )60&b$>@ )60&b1&(b )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25' w g12(1&(b +ljk
electrical characteristics stm32f20xxx 144/179 docid15818 rev 12 figure 68. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are driven (bits 8...15 remains hi-z). figure 69. pc card/compactflash controll er waveforms for i/o space read access w z1:( w y1&(b$ w g15(*1&(b w k1&(b$, w k1&(b15(* w y1:(' dle )60&b1:( )60&b12( )60&b'>@ )60&b$>@ )60&b1&(b )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25' w g1:(1&(b +ljk w g1&(b1:( w g1,25'1&(b w z1,25' w vx'1,25' w g1,25'' w y1&([$ w k1&(b$, dl% )60&b1:( )60&b12( )60&b'>@ )60&b$>@ )60&b1&(b )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25'
docid15818 rev 12 145/179 stm32f20xxx electrical characteristics 178 figure 70. pc card/compactflash controller waveforms for i/o space write access w g1&(b1,2:5 w z1,2:5 w y1&([$ w k1&(b$, w k1,2:5' $77[+,= w y1,2:5' dlf )60&b1:( )60&b12( )60&b'>@ )60&b$>@ )60&b1&(b )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25' table 80. switching characteristics for pc card/cf read and write cycles in attribute/common space (1)(2) symbol parameter min max unit t v(ncex-a) fsmc_ncex low to fsmc_ay valid - 0 ns t h(ncex_ai) fsmc_ncex high to fsmc_ax invalid 4 - ns t d(nreg-ncex) fsmc_ncex low to fsmc_nreg valid - 3.5 ns t h(ncex-nreg) fsmc_ncex high to fsmc_nreg invalid t hclk + 4 - ns t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk + 1 ns t d(ncex-noe) fsmc_ncex low to fsmc_noe low - 5t hclk ns t w(noe) fsmc_noe low width 8t hclk ? 0.5 8t hclk + 1 ns t d(noe_ncex) fsmc_noe high to fsmc_ncex high 5t hclk + 2.5 - ns t su (d-noe) fsmc_d[15:0] valid data before fsmc_noe high 4 - ns t h (n0e-d) fsmc_n0e high to fsmc_d[15:0] invalid 2 - ns t w(nwe) fsmc_nwe low width 8t hclk - 1 8t hclk + 4 ns t d(nwe_ncex ) fsmc_nwe high to fsmc_ncex high 5t hclk + 1.5 ns t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5hclk+ 1 ns t v (nwe-d) fsmc_nwe low to fsmc_d[15:0] valid - 0 ns t h (nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid 8 t hclk -ns t d (d-nwe) fsmc_d[15:0] valid before fsmc_nwe high 13t hclk -ns 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production.
electrical characteristics stm32f20xxx 146/179 docid15818 rev 12 nand controller waveforms and timings figure 71 through figure 74 represent synchronous waveforms, together with table 82 and table 83 provides the corresponding timings. the results shown in this table are obtained with the following fsmc configuration: ? com.fsmc_setuptime = 0x01; ? com.fsmc_waitsetuptime = 0x03; ? com.fsmc_holdsetuptime = 0x02; ? com.fsmc_hizsetuptime = 0x01; ? att.fsmc_setuptime = 0x01; ? att.fsmc_waitsetuptime = 0x03; ? att.fsmc_holdsetuptime = 0x02; ? att.fsmc_hizsetuptime = 0x01; ? bank = fsmc_bank_nand; ? memorydatawidth = fsmc_memorydatawidth_16b; ? ecc = fsmc_ecc_enable; ? eccpagesize = fsmc_eccpagesize_512bytes; ? tclrsetuptime = 0; ? tarsetuptime = 0; in all timing tables, the t hclk is the hclk clock period. table 81. switching characteristics for pc card/cf read and write cycles in i/o space (1)(2) symbol parameter min max unit t w(niowr) fsmc_niowr low width 8t hclk - 0.5 - ns t v(niowr-d) fsmc_niowr low to fsmc_d[15:0] valid - 5t hclk - 1 ns t h(niowr-d) fsmc_niowr high to fsmc_d[15:0] invalid 8t hclk - 3 - ns t d(nce4_1-niowr) fsmc_nce4_1 low to fsmc_niowr valid - 5t hclk + 1.5 ns t h(ncex-niowr) fsmc_ncex high to fsmc_niowr invalid 5t hclk -ns t d(niord-ncex) fsmc_ncex low to fsmc_niord valid - 5t hclk + 1 ns t h(ncex-niord) fsmc_ncex high to fsmc_niord) valid 5t hclk ? 0.5 - ns t w(niord) fsmc_niord low width 8t hclk + 1 - ns t su(d-niord) fsmc_d[15:0] valid before fsmc_niord high 9.5 ns t d(niord-d) fsmc_d[15:0] valid after fsmc_niord high 0 ns 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production.
docid15818 rev 12 147/179 stm32f20xxx electrical characteristics 178 figure 71. nand controller waveforms for read access figure 72. nand controller waveforms for write access &3-#?.7% &3-#?./%.2% &3-#?$;= t su$ ./% t h./% $ aic !,%&3-#?! #,%&3-#?! &3-#?.#%x t d!,% ./% t h./% !,% t h.7% $ t v.7% $ aic &3-#?.7% &3-#?./%.2% &3-#?$;= !,%&3-#?! #,%&3-#?! &3-#?.#%x t d!,% .7% t h.7% !,%
electrical characteristics stm32f20xxx 148/179 docid15818 rev 12 figure 73. nand controller waveforms for common memory read access figure 74. nand controller wavefo rms for common memory write access table 82. switching characterist ics for nand flash read cycles (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production. symbol parameter min max unit t w(n0e) fsmc_noe low width 4t hclk - 1 4t hclk + 2 ns t su(d-noe) fsmc_d[15-0] valid data before fsmc_noe high 9-ns t h(noe-d ) fsmc_d[15-0] valid data after fsmc_noe high 3 - ns t d(ale-noe) fsmc_ale valid before fsmc_noe low - 3t hclk ns t h(noe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk + 2 - ns )60&b1:( )60&b1 2( )60&b'>@ w z12( w vx'12( w k12(' dlf $/()60&b$ &/()60&b$ )60&b1&([ w g$/(12( w k12($/( t w.7% t h.7% $ t v.7% $ aic &3-#?.7% &3-#?. /% &3-#?$;= t d$ .7% !,%&3-#?! #,%&3-#?! &3-#?.#%x t d!,% ./% t h./% !,%
docid15818 rev 12 149/179 stm32f20xxx electrical characteristics 178 6.3.26 camera interface (d cmi) timing specifications 6.3.27 sd/sdio mmc card host in terface (sdio) characteristics unless otherwise specified, the parameters given in table 85 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 14 . refer to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (d[7:0], cmd, ck). figure 75. sdio high-speed mode table 83. switching characteristics for nand flash write cycles (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results, not tested in production. symbol parameter min max unit t w(nwe) fsmc_nwe low width 4t hclk - 1 4t hclk + 3 ns t v(nwe-d) fsmc_nwe low to fsmc_d[15-0] valid - 0 ns t h(nwe-d) fsmc_nwe high to fsmc_d[15-0] invalid 3t hclk -ns t d(d-nwe) fsmc_d[15-0] valid before fsmc_nwe high 5t hclk -ns t d(ale-nwe) fsmc_ale valid before fsmc_nwe low - 3t hclk + 2 ns t h(nwe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk - 2 - ns table 84. dcmi characteristics symbol parameter conditions min max - frequency ratio dcmi_pixclk/ f hclk dcmi_pixclk= 48 mhz 0.4 t 7#+( #+ $#-$ output $#-$ input t # t 7#+, t /6 t /( t )35 t )( t f t r ai
electrical characteristics stm32f20xxx 150/179 docid15818 rev 12 figure 76. sd default mode 6.3.28 rtc characteristics table 85. sd / mmc characteristics symbol parameter conditions min max unit f pp clock frequency in data transfer mode c l 30 pf 0 48 mhz - sdio_ck/f pclk2 frequency ratio - - 8/3 - t w(ckl) clock low time, f pp = 16 mhz c l 30 pf 32 ns t w(ckh) clock high time, f pp = 16 mhz c l 30 pf 31 t r clock rise time c l 30 pf 3.5 t f clock fall time c l 30 pf 5 cmd, d inputs (referenced to ck) t isu input setup time c l 30 pf 2 ns t ih input hold time c l 30 pf 0 cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time c l 30 pf 6 ns t oh output hold time c l 30 pf 0.3 cmd, d outputs (referenced to ck) in sd default mode (1) 1. refer to sdio_clkcr, the sdi clock control register to control the ck output. t ovd output valid default time c l 30 pf 7 ns t ohd output hold default time c l 30 pf 0.5 ai #+ $#-$ output t /6$ t /($ table 86. rtc characteristics symbol parameter conditions min max -f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4-
docid15818 rev 12 151/179 stm32f20xxx package characteristics 178 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1.1 lqfp64, 10 x 10 mm 64 pin low-profile quad flat package figure 77. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline 1. drawing is not to scale. :b0(b9 $ $ $ 6($7,1*3/$1( fff & e & f $ / / . ,'(17,),&$7,21 3,1 ' ' ' h ( ( ( *$8*(3/$1( pp table 87. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106
package characteristics stm32f20xxx 152/179 docid15818 rev 12 figure 78. recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. c 0.090 - 0.200 0.0035 - 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3937 0.3937 0.4016 d3 - 7.500 - - 0.2953 - e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3937 0.3937 0.4016 e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 87. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max aic
docid15818 rev 12 153/179 stm32f20xxx package characteristics 178 7.1.2 wlcsp64+2 - 0.400 mm pitch wafer level chip size package figure 79. wlcsp64+2 - 0.400 mm pitch wafer level chip size package outline 1. drawing is not to scale. $);b0(b9 %xpsvlgh 6lghylhz 'hwdlo$ :dihuedfnvlgh $edooorfdwlrq $ 'hwdlo$ urwdwhge\?& hhh ' 6hdwlqjsodqh $ $ e ( h h h * ) h $ table 88. wlcsp64+2 - 0.400 mm pitch wafer level chip size package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.540 0.570 0.600 0.0213 0.0224 0.0236 a1 - 0.190 - - 0.0075 - a2 - 0.380 - - 0.0150 - a3 - 0.025 - - 0.0010 - b 0.240 0.270 0.300 0.0094 0.0106 0.0118 d 3.604 3.639 3.674 0.1419 0.1433 0.1446 e 3.936 3.971 4.006 0.1550 0.1563 0.1577 e - 0.400 - - 0.0157 - e1 - 3.200 - - 0.1260 - e2 - 3.200 - - 0.1260 -
package characteristics stm32f20xxx 154/179 docid15818 rev 12 7.1.3 lqfp100, 14 x 14 mm 100-pin low-profile quad flat package figure 80. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline 1. drawing is not to scale. f - 0.220 - - 0.0087 - g - 0.386 - - 0.0152 - eee - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 88. wlcsp64+2 - 0.400 mm pitch wafer level chip size package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).' 0,!.% $ $ $ % % % + ccc # # ,?-%?6 ! ! ! , , c b !
docid15818 rev 12 155/179 stm32f20xxx package characteristics 178 table 89. lqpf100 ? 14 x 14 mm 100-pin low- profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f20xxx 156/179 docid15818 rev 12 figure 81. recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. device marking figure 82. lqfp100 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. ai 06y9 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 'dwhfrgh 3lq lqghqwlilhu 670) 9)7; < :: 2swlrqdojdwhpdun
docid15818 rev 12 157/179 stm32f20xxx package characteristics 178 7.1.4 lqfp144, 20 x 20 mm 144-pin low-profile quad flat package figure 83. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline 1. drawing is not to scale. e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).' 0,!.% $ $ $ % % % + ccc # # !?-%?6 ! ! ! , , c b ! table 90. lqfp144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 21.800 22.000 22.2 00 0.8583 0.8661 0.874 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 - 17.500 - - 0.689 -
package characteristics stm32f20xxx 158/179 docid15818 rev 12 figure 84. recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 90. lqfp144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max aic
docid15818 rev 12 159/179 stm32f20xxx package characteristics 178 device marking figure 85. lqfp144 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 'dwhfrgh 3lqlghqwlilhu 670)=*7 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh <:: 2swlrqdojdwhpdun
package characteristics stm32f20xxx 160/179 docid15818 rev 12 7.1.5 lqfp176, 24 24 176-pin low profile quad flat package figure 86. lqfp176 - low profile quad flat package 24 24 1.4 mm, package outline 1. drawing is not to scale. table 91. lqfp176 - low profile quad flat package 24 24 1.4 mm package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 - 1.450 0.0531 - 0.0571 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 23.900 - 24.100 0.9409 - 0.9488 e 23.900 - 24.100 0.9409 - 0.9488 4?-%?6 ! ! e % (% $ ($ :$ :% b mm gaugeplane ! , , k c )$%.4)&)#!4)/. 0). 3eatingplane # !
docid15818 rev 12 161/179 stm32f20xxx package characteristics 178 e - 0.500 - - 0.0197 - hd 25.900 - 26.100 1.0197 - 1.0276 he 25.900 26.100 1.0197 1.0276 l (2) 0.450 0.750 0.0177 0.0295 l1 1.000 0.0394 zd 1.250 0.0492 ze 1.250 0.0492 k0707 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. l dimension is measured at gauge pl ane at 0.25 mm above the seating plane. table 91. lqfp176 - low profile quad flat package 24 24 1.4 mm package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max
package characteristics stm32f20xxx 162/179 docid15818 rev 12 figure 87. lqfp176 recommended footprint 1. dimensions are expr essed in millimeters. 4?&0?6
docid15818 rev 12 163/179 stm32f20xxx package characteristics 178 7.1.6 ufbga176+25 10 10 mm ultra th in fine pitch ba ll grid array figure 88. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline 1. drawing is not to scale. $(b0(b9 6hdwlqjsodqh $ & ggg $ $ h ) ) h 5 $ %277209,(: ( ' 7239,(: ?eedoov % $ % hhh ? 0 iii ? 0 & & $ & $edoo lghqwlilhu $edoo lqgh[duhd e table 92. ufbga176+25 - ultra thin fine pitch ba ll grid array 10 10 0.6 mm mechanical data symbol millimeters inches (1) min typ max min typ max a 0.460 0.530 0.600 0. 0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.002 0.0031 0.0043 a2 0.400 0.450 0.500 0. 0157 0.0177 0.0197 b 0.230 0.280 0.330 0. 0091 0.0110 0.0130 d 9.950 10.000 10.050 0.3917 0.3937 0.3957 e 9.950 10.000 10.050 0.3917 0.3937 0.3957 e - 0.650 - - 0.0256 - f 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f20xxx 164/179 docid15818 rev 12 7.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 93. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp 64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient wlcsp64+2 - 0.400 mm pitch 51 thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 46 thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 40 thermal resistance junction-ambient lqfp176 - 24 24 mm / 0.5 mm pitch 38 thermal resistance junction-ambient ufbga176 - 10 10 mm / 0.5 mm pitch 39
docid15818 rev 12 165/179 stm32f20xxx part numbering 178 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 94. ordering information scheme example: stm32 f 205 r e t 6 vxxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 205 = stm32f20x, connectivity 207= stm32f20x, connectivity, camera interface, ethernet pin count r = 64 pins or 66 pins (1) v = 100 pins z = 144 pins i = 176 pins flash memory size b = 128 kbytes of flash memory c = 256 kbytes of flash memory e = 512 kbytes of flash memory f = 768 kbytes of flash memory g = 1024 kbytes of flash memory package t = lqfp h = ufbga y = wlcsp temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. software option internal code or blank options xxx = programmed parts tr = tape and reel 1. the 66 pins is availabl e on wlcsp package only.
revision history stm32f20xxx 166/179 docid15818 rev 12 9 revision history table 95. document revision history date revision changes 05-jun-2009 1 initial release. 09-oct-2009 2 document status promoted from target specification to preliminary data. in table 8: stm32f20x pin and ball definitions : ? note 4 updated ?v dd_sa and v dd_3 pins inverted ( figure 12: stm32f20x lqfp100 pinout , figure 13: stm32f20x lqfp144 pinout and figure 14: stm32f20x lqfp176 pinout corrected accordingly). section 7.1: package mechanical data changed to lqfp with no exposed pad. 01-feb-2010 3 lfbga144 package removed. stm32f203xx part numbers removed. part numbers with 128 and 256 kbyte flash densities added. encryption features removed. pc13-tamper-rtc renamed to pc13-rtc_af1 and pi8-tamper- rtc renamed to pi8-rtc_af2. 13-jul-2010 4 renamed high-speed sram, system sram. removed combination: 128 kbytes flash memory in lqfp144. added ufbga176 package. added note 1 related to lqfp176 package in ta ble 2 , figure 14 , and table 94 . added information on art accelerator and audio pll (plli2s). added table 6: usart feature comparison . several updates on table 8: stm32f20x pin and ball definitions and table 10: alternate function mapping . adc, dac, oscillator, rtc_af, wkup and vbus signals removed from alternate functions and moved to the ?other functions? column in table 8: stm32f20x pin and ball definitions . traceswo added in figure 4: stm32f20x block diagram , table 8: stm32f20x pin and ball definitions , and table 10: alternate function mapping . xtal oscillator frequency updated on cover page, in figure 4: stm32f20x block diagram and in section 3.11: external interrupt/event controller (exti) . updated list of peripherals used for boot mode in section 3.13: boot modes . added regulator bypass mode in section 3.16: voltage regulator , and section 6.3.4: operating conditions at power-up / power-down (regulator off) . updated section 3.17: real-time clock (rtc), backup sram and backup registers . added note note: in section 3.18: low-power modes . added spi ti protocol in section 3.23: serial peripheral interface (spi) .
docid15818 rev 12 167/179 stm32f20xxx revision history 178 13-jul-2010 4 (continued) added usb otg_fs features in section 3.28: universal serial bus on- the-go full-speed (otg_fs) . updated v cap_1 and v cap_2 capacitor value to 2.2 f in figure 19: power supply scheme . removed dac, modified adc limitations, and updated i/o compensation for 1.8 to 2.1 v range in table 15: limitations depending on the operating power supply range . added v borl , v borm , v borh and i rush in table 19: embedded reset and power control block characteristics . removed table typical current consumption in sleep mode with flash memory in deep power down mode . merged typical and maximum current consumption sections and added table 21: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) , table 20: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram, table 22: typical and maximum current consumption in sleep mode, table 23: typical and maximum current consumptions in stop mode, table 24: typical and maximum current consumptions in standby mode , and table 25: typical and maximum current consumptions in vbat mode . update table 34: main pll characteristics and added section 6.3.11: pll spread spectrum clock generation (sscg) characteristics . added note 8 for cio in table 48: i/o ac characteristics . updated section 6.3.18: tim timer characteristics . added t nrst_out in table 49: nrst pin characteristics . updated table 52: i2c characteristics . removed 8-bit data in and data out waveforms from figure 48: ulpi timing diagram . removed note related to adc calibration in table 67 . section 6.3.20: 12-bit adc characteristics : adc characteristics tables merged into one single table; tables adc conversion time and adc accuracy removed. updated table 68: dac characteristics . updated section 6.3.22: temperatur e sensor characteristics and section 6.3.23: vbat monitoring characteristics . update section 6.3.26: camera interfac e (dcmi) timing specifications . added section 6.3.27: sd/sdio mmc card host interface (sdio) characteristics , and section 6.3.28: rt c characteristics . added section 7.2: thermal characteristics . updated table 91: lqfp176 - low profile quad flat package 24 24 1.4 mm package mechanical data and figure 86: lqfp176 - low profile quad flat package 24 24 1.4 mm, package outline . changed tape and reel code to tx in table 94: ordering information scheme . added table 101: main applications versus package for stm32f2xxx microcontrollers . updated figures in appendix a.2: usb otg full speed (fs) interface solutions and a.3: usb otg high speed (hs) interface solutions . updated figure 94: audio player solution using pll, plli2s, usb and 1 crystal and figure 95: audio pll (plli2s) providing accurate i2s clock . table 95. document revision history (continued) date revision changes
revision history stm32f20xxx 168/179 docid15818 rev 12 25-nov-2010 5 update i/os in section : features . added wlcsp64+2 package. added note 1 related to lqfp176 on cover page. added trademark for art accelerator. updated section 3.2: adaptive real-time memory acce lerator (art accelerator?) . updated figure 5: multi-ahb matrix . added case of bor inactivation using irroff on wlcsp devices in section 3.15: power supply supervisor . reworked section 3.16: voltage regulator to clarify regulator off modes. renamed pdroff, irroff in the whole document. added section 3.19: vbat operation . updated lin and irda features for uart4/5 in table 6: usart feature comparison . table 8: stm32f20x pin and ball definitions : modified v dd_3 pin, and added note related to the fsmc _nl pin; renamed bypass-reg regoff, and add irroff pin; renamed usart4/5 uart4/5. usart4 pins renamed uart4. changed v ss_sa to v ss , and v dd_sa pin reserved for future use. updated maximum hse crystal frequency to 26 mhz. section 6.2: absolute maximum ratings : updated v in minimum and maximum values and note related to five-volt tolerant inputs in table 11: voltage characteristics . updated i inj(pin) maximum values and related notes in table 12: current characteristics . updated v dda minimum value in table 14: general operating conditions . added note 2 and updated maximum cpu frequency in table 15: limitations depending on the operating power supply range , and added figure 21: number of wait states versus fcpu and vdd range . added brownout level 1, 2, and 3 thresholds in table 19: embedded reset and power control block characteristics . changed f osc_in maximum value in table 30: hse 4-26 mhz oscillator characteristics . changed f pll_in maximum value in table 34: main pll characteristics , and updated jitter parameters in table 35: plli2s (audio pll) characteristics . section 6.3.16: i/o po rt characteristics : updated v ih and v il in table 48: i/o ac characteristics . added note 1 below table 47: output voltage characteristics . updated r pd and r pu parameter description in table 57: usb otg fs dc electrical characteristics . updated v ref+ minimum value in table 66: adc characteristics . updated table 71: embedded internal reference voltage . removed ethernet and usb2 for 64-pin devices in ta ble 10 1: main applications versus package for stm32f2xxx microcontrollers . added a.2: usb otg full speed (fs) interface solutions , removed ?otg fs connection with exte rnal phy? figure, updated figure 87 , figure 88 , and figure 90 to add stulpi01b. table 95. document revision history (continued) date revision changes
docid15818 rev 12 169/179 stm32f20xxx revision history 178 22-apr-2011 6 changed datasheet status to ?full datasheet?. introduced concept of sram1 and sram2. lqfp176 package now in production and offered only for 256 kbyte and 1 mbyte devices. availability of wlcsp64+2 package limited to 512 kbyte and 1 mbyte devices. updated figure 3: compatible board design between stm32f10xx and stm32f2xx for lqfp144 package and figure 2: compatible board design between stm32f10xx and stm32f2xx for lqfp100 package . added camera interface for stm32f207vx devices in table 2: stm32f205xx features and peripheral counts . removed 16 mhz internal rc oscillator accuracy in section 3.12: clocks and startup . updated section 3.16: voltage regulator . modified i 2 s sampling frequency range in section 3.12: clocks and startup , section 3.24: inter-integrated sound (i2s) , and section 3.30: audio pll (plli2s) . updated section 3.17: real-time clock (rtc), backup sram and backup registers and description of tim2 and tim5 in section 3.20.2: general-purpose timers (timx) . modified maximum baud rate (oversampling by 16) for usart1 in table 6: usart feature comparison . updated note related to rfu pin below figure 12: stm32f20x lqfp100 pinout , figure 13: stm32f20x lqfp144 pinout , figure 14: stm32f20x lqfp176 pinout , figure 15: stm32f20x ufbga176 ballout , and table 8: stm32f20x pin and ball definitions . in table 8: stm32f20x pin and ball definitions ,:changed i2s2_ck and i2s3_ck to i2s2_sck and i2s3_sck, respectively; added pa15 and tt (3.6 v tolerant i/o). added rtc_50hz as pb15 alternate function in table 8: stm32f20x pin and ball definitions and table 10: alternate function mapping . removed eth _rmii_tx_clk for pc3/af11 in table 10: alternate function mapping . updated table 11: voltage characteristics and table 12: current characteristics . t stg updated to ?65 to +150 in table 13: thermal characteristics . added cext, esl, and esr in table 14: general operating conditions as well as section 6.3.2: vcap1/vcap2 external capacitor . modified note 4 in table 15: limitations depending on the operating power supply range . updated table 17: operating conditions at power-up / power-down (regulator on) , and table 18: operating conditions at power-up / power-down (regulator off) . added osc_out pin in figure 17: pin loading conditions . and figure 18: pin input voltage . updated figure 19: power supply scheme to add irroff and regoff pins and modified notes. updated v pvd , v bor1 , v bor2 , v bor3 , t rsttempo typical value, and i rush , added e rush and note 2 in table 19: embedded reset and power control block characteristics . table 95. document revision history (continued) date revision changes
revision history stm32f20xxx 170/179 docid15818 rev 12 22-apr-2011 6 (continued) updated typical and maximum current consumption conditions, as well as table 21: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) and table 20: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram . added figure 23 , figure 24 , figure 25 , and figure 26 . updated table 22: typical and maximum current consumption in sleep mode , and added figure 27 and figure 28 . updated table 23: typical and maximum current consumptions in stop mode . added figure 29: typical current consumption vs temperature in stop mode . updated table 24: typical and maximum current consumptions in standby mode and table 25: typical and maximum current consumptions in vbat mode . updated on-chip peripheral current consumption conditions and table 26: peripheral current consumption . updated t wustdby and t wustop , and added note 3 in table 27: low- power mode wakeup timings . maximum f hse_ext and minimum t w(hse) values updated in table 28: high-speed external user clock characteristics . updated c and g m in table 30: hse 4-26 mhz oscillator characteristics . updated r f , i 2 , g m , and t su(lse) in table 31: lse oscillator characteristics (flse = 32.768 khz) . added note 1 and updated acc hsi , idd (hsi , and t su(hsi) in ta ble 32 : hsi oscillator characteristics . added figure 34: acchsi versus temperature . updated f lsi , t su(lsi) and idd (lsi) in table 33: lsi oscillator characteristics . added figure 35: acclsi versus temperature table 34: main pll characteristics : removed note 1, updated t lock , jitter, idd (pll) and idd a(pll) , added note 2 for f pll_in minimum and maximum values. table 35: plli2s (audio pll) characteristics : removed note 1, updated t lock , jitter, idd (plli2s) and idd a(plli2s) , added note 2 for f plli2s_in minimum and maximum values. added note 1 in table 36: sscg parameters constraint . updated table 37: flash memory characteristics . modified table 38: flash memory programming and added note 2 for t prog . updated t prog and added note 1 in table 39: flash memory programming with vpp . modified figure 40: recommended nrst pin protection . updated table 42: emi characteristics and emi monitoring conditions in section : electromagnetic interference (emi) . added note 2 related to v esd(hbm) in table 43: esd absolute maximum ratings . updated table 48: i/o ac characteristics . added section 6.3.15: i/o current injection characteristics . modified maximum frequency values and conditions in table 48: i/o ac characteristics . updated t res(tim) in table 50: characteristics of timx connected to the apb1 domain . modified t res(tim) and f ext table 51: characteristics of timx connected to the apb2 domain . table 95. document revision history (continued) date revision changes
docid15818 rev 12 171/179 stm32f20xxx revision history 178 22-apr-2011 6 (continued) changed t w(sckh) to t w(sclh) , t w(sckl) to t w(scll) , t r(sck) to t r(scl) , and t f(sck) to t f(scl) in table 52: i2c characteristics and in figure 41: i2c bus ac waveforms and measurement circuit . added table 57: usb otg fs dc electrical characteristics and updated table 58: usb otg fs electrical characteristics . updated v dd minimum value in table 62: ethernet dc electrical characteristics . updated table 66: adc characteristics and r ain equation. updated r ain equation. updated table 68: dac characteristics . updated t start in table 69: temperature sensor characteristics . updated r typical value in table 70: vbat monitoring characteristics . updated table 71: embedded internal reference voltage . modified fsmc_noe waveform in figure 57: asynchronous non- multiplexed sram/psram /nor read waveforms . shifted end of fsmc_nex/nadv/addresses/nwe/noe/nwait of a half fsmc_clk period, changed t d(clkh-nexh ) to t d(clkl-nexh) , t d(clkh-aiv) to t d(clkl- aiv) , t d(clkh-noeh) to t d(clkl-noeh) , and t d(clkh-nweh) to t d(clkl- nweh) , and updated data latency from 1 to 0 in figure 61: synchronous multiplexed nor/psram read timings , figure 62: synchronous multiplexed psram write timings , figure 63: synchronous non-multiplexed nor/psram read timings , and figure 64: synchronous non-multiplexed psram write timings , changed t d(clkh-nexh ) to t d(clkl-nexh) , t d(clkh-aiv) to t d(clkl-aiv) , t d(clkh-noeh) to t d(clkl-noeh) , t d(clkh-nweh) to t d(clkl-nweh) , and modified t w(clk) minimum value in table 76 , table 77 , table 78 , and ta ble 79 . updated note 2 in ta ble 7 2 , table 73 , table 74 , table 75 , table 76 , ta ble 77 , table 78 , and table 79 . modified t h(niowr-d) in figure 70: pc card/compactflash controller waveforms for i/o space write access . modified fsmc_ncex signal in figure 71: nand controller waveforms for read access , figure 72: nand controller waveforms for write access , figure 73: nand controller waveforms for common memory read access , and figure 74: nand controller waveforms for common memory write access specified full speed (fs) mode for figure 89: usb otg hs peripheral-only connection in fs mode and figure 90: usb otg hs host-only connection in fs mode . table 95. document revision history (continued) date revision changes
revision history stm32f20xxx 172/179 docid15818 rev 12 14-jun-2011 7 added sdio in table 2: stm32f205xx features and peripheral counts . updated v in for 5v tolerant pins in table 11: voltage characteristics . updated jitter parameters description in table 34: main pll characteristics . remove jitter values for system clock in table 35: plli2s (audio pll) characteristics . updated table 42: emi characteristics . update note 2 in table 52: i2c characteristics . updated avg_slope typical value and t s_temp minimum value in table 69: temperature sensor characteristics . updated t s_vbat minimum value in table 70: vbat monitoring characteristics . updated t s_vrefint mimimum value in table 71: embedded internal reference voltage . added software option in section 8: part numbering . in table 101: main app lications versus package for stm32f2xxx microcontrollers , renamed usb1 and usb2, usb otg fs and usb otg hs, respectively; and removed usb otg fs and camera interface for 64-pin package; added usb otg hs on 64-pin package; added note 1 and note 2 . 20-dec-2011 8 updated sdio register addresses in figure 16: memory map . updated figure 3: compatible board design between stm32f10xx and stm32f2xx for lqfp144 package , figure 2: compatible board design between stm32f10xx and stm32f2xx for lqfp100 package , figure 1: compatible board design between stm32f10xx and stm32f2xx for lqfp64 package , and added figure 4: compatible board design between stm32f10xx and stm32f2xx for lqfp176 package . updated section 3.3: memory protection unit . updated section 3.6: embedded sram . updated section 3.28: universal seri al bus on-the-go full-speed (otg_fs) to remove external fs otg phy support. in table 8: stm32f20x pin and ball definitions : changed spi2_mck and spi3_mck to i2s2_mck and i2s3_mck, respectively. added eth _rmii_tx_en atlter nate functi on to pg11. added eventout in the list of alternate functions for i/o pin/balls. removed otg_fs_sda, otg_fs_scl and otg_fs_intn alternate functions. in table 10: alternate function mapping : changed i2s3_sck to i2s3_mck for pc7/af6, added fsmc_nce3 for pg9, fsmc_ne3 for pg10, and fsmc_nce2 for pd7. removed otg_fs_sda, otg_fs_scl and otg_fs_intn al ternate functions. changed i2s3_sck into i2s3_mck for pc7/af6. updated peripherals corresponding to af12. removed cext and esr from table 14: general operating conditions . table 95. document revision history (continued) date revision changes
docid15818 rev 12 173/179 stm32f20xxx revision history 178 20-dec-2011 8 (continued) added maximum power consumption at t a =25 c in table 23: typical and maximum current consumptions in stop mode . updated md minimum value in table 36: sscg parameters constraint . added examples in section 6.3.11: pll spread spectrum clock generation (sscg) characteristics . updated table 54: spi characteristics and table 55: i2s characteristics . updated figure 48: ulpi timing diagram and table 61: ulpi timing . updated table 63: dynamics characterist ics: ethernet mac signals for smi , table 64: dynamics characterist ics: ethernet mac signals for rmii , and table 65: dynamics characteristics: ethernet mac signals for mii . section 6.3.25: fsmc characteristics : updated table 72 to ta ble 83 , changed c l value to 30 pf, and modified fsmc configuration for asynchronous timings and waveforms. updated figure 62: synchronous multiplexed psram write timings . updated table 84: dcmi characteristics . updated table 92: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data . updated table 94: ordering information scheme . appendix a.2: usb otg full speed (fs) interface solutions : updated figure 87: usb otg fs (full speed) host-only connection and added note 2 , updated figure 88: otg fs (full speed) connection dual-role with internal phy and added note 3 and note 4 , modified figure 89: otg hs (high speed) device connection, host and dual-role in high- speed mode with external phy and added note 2 . appendix a.3: usb otg high speed (hs) interface solutions : removed figures usb otg hs device-only connection in fs mode and usb otg hs host-only connection in fs mode, updated figure 89: otg hs (high speed) device connection, host and dual-role in high- speed mode with external phy . added appendix a.4: ethernet interface solutions . updated disclaimer on last page. 24-apr-2012 9 updated v dd minimum value in section 2: description . updated number of usb otg hs and fs, modified packages for stm32f207ix part numbers, added note 1 related to fsmc and note 2 related to spi/i2s, and updated note 3 in ta ble 2: stm32f205xx features and peripheral counts and ta ble 3: stm32f207xx features and peripheral counts . added note 2 and update tim5 in figure 4: stm32f20x block diagram . updated maximum number of maskable interrupts in section 3.10: nested vectored interrupt controller (nvic) . updated v dd minimum value in section 3.14: powe r supply schemes . updated note a in section 3.16.1: regulator on . removed stm32f205xx in section 3.28: universa l serial bus on-the- go full-speed (otg_fs) . table 95. document revision history (continued) date revision changes
revision history stm32f20xxx 174/179 docid15818 rev 12 24-apr-2012 9 (continued) removed support of i2c for otg phy in section 3.29: universal serial bus on-the-go high-speed (otg_hs) . removed otg_hs_scl, otg_hs_sda, otg_fs_intn in table 8: stm32f20x pin and ball definitions and table 10: alternate function mapping . renamed ph10 alternate function into tim5_ch1 in table 10: alternate function mapping . added table 9: fsmc pin definition . updated note 1 in table 14: general operating conditions , note 2 in table 15: limitations depending on the operating power supply range , and note 1 below figure 21: number of wait states versus fcpu and vdd range . updated v por/pdr in table 19: embedded reset and power control block characteristics . updated typical values in table 24: typical and maximum current consumptions in standby mode and table 25: typical and maximum current consumptions in vbat mode . updated table 30: hse 4-26 mhz oscillator characteristics and table 31: lse oscillator characteristics (flse = 32.768 khz) . updated table 37: flash memory characteristics , table 38: flash memory programming , and table 39: flash memory programming with vpp . updated section : output driving current . updated note 3 and removed note related to minimum hold time value in table 52: i2c characteristics . updated table 64: dynamics characterist ics: ethernet mac signals for rmii . updated note 1 , c adc , i vref+ , and i vdda in table 66: adc characteristics . updated note 3 and note concerning adc accuracy vs. negative injection current in table 67: adc accuracy . updated note 1 in table 68: dac characteristics . updated section figure 88.: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline . appendix a.1: main applications versus package : removed number of address lines for fsmc/nand in table 101: main applications versus package for stm32f2xxx microcontrollers . appendix a.4: ethernet interface solutions : updated figure 92: complete audio player solution 1 and figure 93: complete audio player solution 2 . table 95. document revision history (continued) date revision changes
docid15818 rev 12 175/179 stm32f20xxx revision history 178 29-oct-2012 10 changed minimum supply voltage from 1.65 to 1.8 v. updated number of ahb buses in section 2: description and section 3.12: clocks and startup . removed figure 4. compatible board design between stm32f10xx and stm32f2xx for lqfp176 package. updated note 2 below figure 4: stm32f20x block diagram . changed system memory to system memory + otp in figure 16: memory map . added note 1 below table 16: vcap1/vcap2 operating conditions . updated v dda and v ref+ decouping capacitor in figure 19: power supply scheme and updated note 3 . changed simplex mode into half-duplex mode in section 3.24: inter- integrated sound (i2s) . replaced dac1_out and dac2_out by dac_out1 and dac_out2, respectively.changed tim2_ch1/tim2_etr into tim2_ch1_etr for pa0 and pa5 in table 10: alternate function mapping . updated note applying to i dd (external clock and all peripheral disabled) in table 21: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) . updated note 3 below table 22: typical and maximum current consumption in sleep mode . removed f hse_ext typical value in table 28: high-speed external user clock characteristics . updated master i2s clock jitter conditions and vlaues in table 35: plli2s (audio pll) characteristics . updated equations in section 6.3.11: pll spread spectrum clock generation (sscg) characteristics . swapped ttl and cmos port conditions for v ol and v oh in ta ble 47 : output voltage characteristics . updated v il(nrst) and v ih(nrst) in table 49: nrst pin characteristics . updated table 54: spi characteristics and table 55: i2s characteristics . removed note 1 related to measurement points below figure 43: spi timing diagram - slave mode and cpha = 1 , figure 44: spi timing diagram - master mode , and figure 45: i2s slave timing diagram (philips protocol)(1) . updated t hc in table 61: ulpi timing . updated figure 49: ethernet smi timing diagram , table 63: dynamics characteristics: ethernet mac signals for smi and table 65: dynamics characteristics: ethernet mac signals for mii . update f trig in table 66: adc characteristics . updated i dda description in table 68: dac characteristics . updated note below figure 54: power supply and reference decoupling (vref+ not connected to vdda) and figure 55: power supply and reference decoupling (vref+ connected to vdda) . table 95. document revision history (continued) date revision changes
revision history stm32f20xxx 176/179 docid15818 rev 12 29-oct-2012 10 (continued) replaced t d(clkl-noel) by t d(clkh-noel) in table 76: synchronous multiplexed nor/psram read timings , table 78: synchronous non- multiplexed nor/psram read timings , figure 61: synchronous multiplexed nor/psram read timings and figure 63: synchronous non-multiplexed nor/psram read timings . added figure 87: lqfp176 recommended footprint . added note 2 below figure 86: regulator off/internal reset on . updated device subfamily in table 94: ordering information scheme . remove reference to note 2 for usb iotg fs in table 101: main applications versus package for stm32f2xxx microcontrollers . table 95. document revision history (continued) date revision changes
docid15818 rev 12 177/179 stm32f20xxx revision history 178 04-nov-2013 11 in the whole document, updated no tes related to wlcsp64+2 usage with irroff set to v dd . updated section 3.14: power supply schemes , section 3.15: power supply supervisor , section 3.16.1: regulator on and section 3.16.2: regulator off . added section 3.16.3: regulator on/off and internal reset on/off availability . added note related to wlcsp64+2 package. restructured rtc features and added reference clock detection in section 3.17: real-time clock (rtc), backup sram and backup registers . added note indicating the package view below figure 10: stm32f20x lqfp64 pinout , figure 12: stm32f20x lqfp100 pinout , figure 13: stm32f20x lqfp144 pinout , and figure 14: stm32f20x lqfp176 pinout . added table 7: legend/abbreviations used in the pinout table . ta ble 8: stm32f20x pin and ball definitions : content reformatted; removed indeces on v ss and v dd ; updated pa4, pa5, pa6, pc4, boot0; replaced dcmi_12 by dcmi_d12, tim8_chin by tim8_ch1n, eth_mii_rx_d0 by eth_mii_rxd0, eth_mii_rx_d1 by eth_mii_rxd1, eth_rmii_rx_d0 by eth_rmii_rxd0, eth_rmii_rx_d1 by eth_rmii_rxd1, and rmii_crs_dv by eth_rmii_crs_dv. table 10: alternate function mapping : replaced fsmc_bln1 by fsmc_nbl1, added even tout as af15 alte rnated fucntion for pc13, pc14, pc15, ph 0, ph1, and pi8. updated figure 17: pin loading conditions and figure 18: pin input voltage . added v in in table 14: general operating conditions . removed note applying to v por/pdr minimum value in ta ble 19 : embedded reset and power control block characteristics . updated notes related to c l1 and c l2 in section : low-speed external clock generated from a crystal/ceramic resonator . updated conditions in table 41: ems characteristics . updated table 42: emi characteristics . updated v il , v ih and v hys in table 46: i/o static characteristics . added section : output driving current and updated figure 39: i/o ac characteristics definition . updated v il(nrst) and v ih(nrst) in table 49: nrst pin characteristics , updated figure 39: i/o ac characteristics definition . removed tests conditions in section : i2c interface characteristics . updated table 52: i2c characteristics and figure 41: i2c bus ac waveforms and measurement circuit . updated i vref+ and i vdda in table 66: adc characteristics . updated offset comments in table 68: dac characteristics . updated minimum t h(clkh-dv) value in table 78: synchronous non- multiplexed nor/psram read timings . table 95. document revision history (continued) date revision changes
revision history stm32f20xxx 178/179 docid15818 rev 12 04-nov-2013 11 (continued) removed appendix a application block diagrams. updated figure 77: lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline and table 87: lqfp64 ? 10 x 10 mm 64 pin low- profile quad flat package mechanical data . updated figure 80: lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline , figure 83: lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline , figure 86: lqfp176 - low profile quad flat package 24 24 1.4 mm, package outline . updated figure 88: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline and figure 88: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline . 27-oct-2014 12 updated v bat voltage range in figure 19: power supply scheme . added caution note in section 6.1.6: power supply scheme . updated v in in table 14: general operating conditions . removed note 1 in table 23: typical and maximum current consumptions in stop mode . updated table 45: i/o current injection susceptibility , section 6.3.16: i/o port characteristics and section 6.3.17: nrst pin characteristics . removed note 3 in table 69: temperature sensor characteristics . updated figure 79: wlcsp64+2 - 0.400 mm pitch wafer level chip size package outline and table 88: wlcsp64+2 - 0.400 mm pitch wafer level chip size package mechanical data . added figure 82: lqfp100 marking (package top view) and figure 85: lqfp144 marking (package top view) . table 95. document revision history (continued) date revision changes
docid15818 rev 12 179/179 stm32f20xxx 179 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of STM32F205VET6

	To Download STM32F205VET6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .